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This patch adds generic code to support Freescale's i.MX27 SoCs.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
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Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.
It has been tested on a i.MX31 PDK board with large page NAND. Small
page NANDs should work as well, but this has not been tested.
Note: The i.MX31 NFC uses a non-standard layout for large page NANDs,
whether this is compatible with a particular setup depends on how
the NAND device is programmed by the flash programmer (e.g. JTAG
debugger).
The patch is based on the work by Maxim Artamonov.
Signed-off-by: Maxim Artamonov <scn1874@yandex.ru>
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
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the lowlevel init sequence is the same so unify it
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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this will allow you to store use it for the env and to boot directly U-Boot from
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The PM9261 board is based on the AT91SAM9261-EK board.
Here is the page on Ronetix website:
http://www.ronetix.at/starter_kit_9261.html
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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optimize a few the RAM init
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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move PSRAM init to pm9263.c
this will allow us after to make the nor lowlevel_init generic
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The SPI flash define is named CONFIG_SF_DEFAULT_SPEED, not
CONFIG_SF_DEFAULT_HZ, so fix the typos in the Blackfin boards.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The latest version of U-Boot got a bit fatter in the BSS section which
caused overflows in the RAM region, so increase the monitor size.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The SPI flash layer is much stricter about sector usage than the eeprom
layer we used to use, so update the env settings to better match the
sector alignment of the flashes we use.
Signed-off-by: Vivi Li <vivi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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All drivers need to be converted to CONFIG_NET_MULTI.
This patch converts the dm9000 driver.
Signed-off-by: Thomas Smits <ts.smits@gmail.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This patch adds a egiga driver for the Marvell Kirkwood SoC's.
Contributors:
Yotam Admon <yotam@marvell.com>
Michael Blostein <michaelbl@marvell.com
Reviewed-by: Ronen Shitrit <rshitrit@marvell.com>
Acked-by: Stefan Rose <sr@denx.de>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Different flavours of DaVinci SOC's have differences in their EMAC IP
This patch does the following
1) Updates base addresses for DM365
2) Updates MDIO frequencies for DM365 and DM646x
3) Update EMAC wrapper registers for DM365 and DM646x
Patch applies to u-boot-net git. the EMAC driver itself
will be updated shortly to add support for DM365 and DM646x
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Added CONFIG_NET_MULTI to all Davinci boards
Removed all calls to Davinci network driver from board code
Added cpu_eth_init() to cpu/arm926ejs/cpu.c
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Chips supported:-
1. 88E6161 6 port gbe swtich with 5 integrated PHYs
2. 88E6165 6 port gbe swtich with 5 integrated PHYs
2. 88E6132 3 port gbe swtich with 2 integrated PHYs
Platform specific configuration supported for:-
default or router port vlan configuration
led_init configuration
mdip/n polarity reversal configuration
Note: This driver is supported and tested against
kirkwood egiga interface
Contributors:
Yotam Admon <yotam@marvell.com>
Michael Blostein <michaelbl@marvell.com
Reviewed by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Zach LeRoy <zleroy@xes-inc.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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All the Blackfin linker scripts were duplicated across the board dirs with
no difference save from the semi-often used ENV_IS_EMBEDDED option. So
unify all of them in the lib_blackfin/ dir and for the few boards that
need to embedded the environment directly, add a LDS_BOARD_TEXT define for
them to customize via their board config file. This is much simpler than
forcing them to duplicate the rest of the linker script.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BF51xF parts have an internal SST SPI flash, so make sure the driver is
enabled by default so we can access it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The Blackfin port was using asm/blackfin-config-{pre,post}.h to setup
common Blackfin board defines. The common method now is to use config.h,
so convert blackfin-config-post.h to that. Rename the still Blackfin
specific blackfin-config-pre.h to config-pre.h so the naming conventions
at least line up.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Allow boards to easily override the root= and default bootcmd, allow
people to tweak the file used in default bootcmds at runtime via one env
var, and add a stock nandboot command.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Newer Blackfin parts can an on-chip ROM that can boot LDRs over SPI flashes,
so add a new 'spibootldr' command to take advantage of it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Add defines similar to those already used for the the 86xx architecture.
This will ease sharing of PCI code between the 85xx and 86xx
architectures.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:
85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register. These bits
only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
status register. We may as well clear all 32 bits of the register...
86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
the controller
- Clear the channel start bit in the DMA mode register after a transfer
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via
UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we
disable UEC6 and UEC8 by default.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <Timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The patch adds support for P2020DS reference platform.
DDR3 interface uses hard-coded initialization rather than SPD
for now and was tested at 667Mhz. Some PIXIS register
definitions and associated code sections need to be fixed.
TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all
tested under u-boot.
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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