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2013-06-26sandbox: Support trace featureSimon Glass
Support tracing on sandbox by adding suitable CONFIG options. To enable it, compile U-Boot with FTRACE=1. The timer functions are marked to skip tracing, since these are called from the tracing code itself, and we want to avoid an infinite loop. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add trace support to generic boardSimon Glass
Add hooks for tracing to generic board, including: - allow early tracing to start early as possible in U-Boot - reserve memory for trace buffer - copy early trace buffer to main trace buffer after relocation - setup full tracing support after relocation Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add trace librarySimon Glass
Add a library which supports tracing of execution using built-in gcc features and a microsecond timer. This can be used to record a list of function which are executed, along with a timestamp for each. Later this information can be sent to the host for processing. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add function to print a number with grouped digitsSimon Glass
Move bootstage's numbering printing code into a generic place so that it can be used by tracing also. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26pci: Convert extern inline functions to static inlineSimon Glass
I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: exynos: enable cros-ec for smdk5250Hung-ying Tyan
This patch initiates cros-ec in board_init() to enable it for smdk5250. This patch depends on the patch in the MMC series that brings in exynos5-dt.c. Refer to http://patchwork.ozlabs.org/patch/240084. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: adds cros_ec keyboard driverHung-ying Tyan
This patch adds the driver for keyboard that's controlled by ChromeOS EC. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: exynos: add SPI support for cros_ecHung-ying Tyan
This patch adds SPI support for carrying out the cros_ec protocol. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: add cros_ec driverHung-ying Tyan
This patch adds the cros_ec driver that implements the protocol for communicating with Google's ChromeOS embedded controller. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2013-06-24net: add Faraday FTMAC110 10/100Mbps ethernet supportKuo-Jung Su
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux. However it has a weird DMA alignment issue: (1) Tx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: O.K (2) Rx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: Invalid!!! Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
2013-06-24net: phy: supplement support for Micrel's KSZ9031SARTRE Leo
Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
2013-06-24ARM: at91sam9n12: add network support with ksz8851_16mllBo Shen
add network support with ksz8851_16mll on at91sam9n12ek board Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-06-24net: ks8851_mll: add ethernet supportRoberto Cerati
The device interface is 16 bits wide. All the available packets are read from the incoming fifo. Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it> Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> [voice.shen@atmel.com: address comments from review results] [voice.shen@atmel.com: clean up for submit] Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
2013-06-24add support for Xilinx 1000BASE-X phy (GTX)Charles Coldwell
commit 39695029bc15041c809df3db4ba19bd729c447fa Author: Charles Coldwell <coldwell@ll.mit.edu> Date: Tue Feb 19 08:27:33 2013 -0500 Changes to support the Xilinx 1000BASE-X phy (GTX/MGT) Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
2013-06-24net: make IPaddr type big endianKim Phillips
for use with sparse. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
2013-06-24bootz: un-staticize do_bootzRob Herring
Make do_bootz available for other functions like do_bootm is. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-06-24phy: export genphy_parse_link()Yegor Yefremov
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2013-06-24net: Add sunxi (Allwinner) wemac driverHenrik Nordström
This patch adds support for the WEMAC, the ethernet controller included in the Allwinner A10 SoC. It will get used in the upcoming A10 board support. From: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2013-06-24ac14xx: rephrase network boot config for developmentGerhard Sittig
- remove the builtin 'rootpath' spec (according to U-Boot project policy) and require user provided environments to contain these - rephrase the evaluation of the 'muster_nr' approach which allows to quickly switch among several network boot setups (make the setting transparent when empty, resulting in default DULG behaviour) - reduce the ARP timeout for faster network boot Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-24ac14xx: use the official product name everywhereGerhard Sittig
remove remaining "k6" code names, switch to the official 'ac14xx' name Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-24ac14xx: remove obsolete board config itemsGerhard Sittig
- use the default baudrate table for serial communication - remove hostname/boofile/rootpath defines which were not referenced elsewhere Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-24ac14xx: cleanup comments in the board supportGerhard Sittig
fix typos, minor rephrasing, remove obsolete notes and TODO items Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-23sf: Add flag status register polling supportJagannadha Sutradharudu Teki
Flag status register polling is required for micron 512Mb flash devices onwards, for performing erase/program operations. Like polling for WIP(Write-In-Progress) bit in read status register, spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control) bit in flag status register. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Add bank addr code in CONFIG_SPI_FLASH_BARJagannadha Sutradharudu Teki
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Read flash bank addr register at probe timeJagannadha Sutradharudu Teki
Read the flash bank addr register to get the state of bank in a perticular flash. and also bank write happens only when there is a change in bank selection from user. bank read only valid for flashes which has > 16Mbytes those are opearted in 3-byte addr mode, each bank occupies 16Mytes. Suppose if the flash has 64Mbytes size consists of 4 banks like bank0, bank1, bank2 and bank3. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Discover the bank addr commandsJagannadha Sutradharudu Teki
Bank/Extended addr commands are specific to particular flash vendor so discover them based on the idocode0. Assign the discovered bank commands to spi_flash members so-that the bank read/write will use their specific operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-06-21remove all references to .dynsymAlbert ARIBAUD
Discard all .dynsym sections from linker scripts Remove all __dynsym_start definitions from linker scripts Remove all __dynsym_start references from the codebase Note: this touches include/asm-generic/sections.h, which is not ARM-specific, but actual uses of __dynsym_start are only in ARM, so this patch can safely go through the ARM repository. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-20powerpc/85xx: Add P1023RDB board supportChunhe Lan
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPLYing Zhang
There will need the environment in SPL for reasons other than network support (in particular, hwconfig contains info for how to set up DDR). Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT for environment in common/Makefile. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/b4860qds: Relax NOR flash teadc timing parameterPrabhakar Kushwaha
Relax parameters to give address latching more time to setup. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/t4qds: Slave module for boot from SRIO and PCIELiu Gang
When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/t4qds: Enable master module for Boot from SRIO and PCIELiu Gang
T4 can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/b4860qds: Slave module for boot from SRIO and PCIELiu Gang
When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/b4860qds: Enable master module for boot from SRIO and PCIELiu Gang
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9131rdb: Update default boot environment settingsPriyanka Jain
BSC9131RDB has 1GB DDR. Out of this, only 880MB is passed on to Linux via bootm_size. Remaining -16MB is reserved for PowerPC-DSP shared control area -128MB is reserved for DSP private area. Also 256MB, out of this 880MB is required for data communication between PowerPC and DSP core. For this bootargs are modified to pass parameter to create 1 hugetlb page of 256MB via default_hugepagesz, hugepagesz and hugepages Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9131rdb: Add DSP side tlb and lawsPriyanka Jain
BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9131rdb: Add targets for Sysclk 100MHzPriyanka Jain
BSC9131RDB supports Sysclk -66MHz if jumper J16 is close (default state) -100MHz if jumper J16 is open Add targets -BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz -BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9132qds:Add NAND boot support using new SPL formatPrabhakar Kushwaha
- Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB, LAW entries as per NAND boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9131rdb:Add NAND boot support using new SPL formatPrabhakar Kushwaha
- Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/p1010rdb:Add NAND boot support using new SPL formatPrabhakar Kushwaha
- defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot - remove nand_spl support for P1010RDB Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399Prabhakar Kushwaha
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20net2big_v2: initialize I2C fan at startupSimon Guinot
This patch ensures minimal cooling for the net2big_v2 by automatically starting the I2C fan (GMT G762) at low speed (2800 RPM). Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2013-06-19Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-06-19Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: spl/Makefile
2013-06-18arm: omap4: panda: Add reading of the board revisionDan Murphy
Detect if we are running on a panda revision A1-A6, or an ES panda board. This can be done by reading the level of GPIOs and checking the processor revisions. This should result in: Panda 4430: GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5 GPIO171, GPIO101, GPIO182: 1 0 1 => A6 Panda ES: GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2 GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3 Set the board name appropriately for the board revision that is detected. Update the findfdt macro to load the a4 device tree binary. Signed-off-by: Dan Murphy <dmurphy@ti.com> [trini: %s/CONTROL_PADCONF_CORE/(*ctrl)->control_padconf_core_base/ and formatting for that] Signed-off-by: Tom Rini <trini@ti.com>
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