summaryrefslogtreecommitdiff
path: root/nand_spl
AgeCommit message (Collapse)Author
2007-06-06ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese
This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese
2007-06-01ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01NAND: Add ECC support to NAND booting support in nand_spl/nand_boot.cStefan Roese
The U-Boot NAND booting support is now extended to support ECC upon loading of the NAND U-Boot image. Tested on AMCC Sequoia (440EPx) and Bamboo (440EP). Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-05ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese
As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05[PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
2006-10-23Fix sequoia separate object direcory building problems.Marian Balakowicz
2006-10-09Coding style cleanupWolfgang Denk
2006-09-12Add NAND environment support for PPC440EPx Sequoia NAND boot configStefan Roese
Patch by Stefan Roese, 12 Sep 2006
2006-09-12Update NAND boot documentationStefan Roese
Patch by Stefan Roese, 12 Sep 2006
2006-09-07Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006