From 07a5cb9d3b9bf9bca9ca207b82f92eac73cbdda8 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Tue, 23 Jul 2019 16:49:32 +0200 Subject: spi: mvebu_a3700_spi: Fix clock prescale computation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The prescaler value computation can yield wrong result if given 0x1f at the beginning: the value is computed to be 0x20, but the maximum value the register can hold 0x1f, so the actual stored value in this case is 0, which is obviously wrong. Set the upper bound of the value to 0x1f with the min macro. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Reviewed-by: Jagan Teki --- drivers/spi/mvebu_a3700_spi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index feeafdceaa..99ad505f24 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -181,10 +181,9 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) data = readl(®->cfg); prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz); - if (prescale > 0x1f) - prescale = 0x1f; - else if (prescale > 0xf) + if (prescale > 0xf) prescale = 0x10 + (prescale + 1) / 2; + prescale = min(prescale, 0x1fu); data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK; data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK; -- cgit