From b3f8e88f3c07f6c72db55faffaaa25990d316c6f Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 13 Aug 2018 14:23:07 +0200 Subject: pinctrl: bcm6838: add pinctrl support Add pinctrl support for broadcom bcm6838 SoC. Signed-off-by: Philippe Reynes --- .../pinctrl/bcm6838-pinctrl.txt | 35 +++++ drivers/pinctrl/broadcom/Kconfig | 8 + drivers/pinctrl/broadcom/Makefile | 1 + drivers/pinctrl/broadcom/pinctrl-bcm6838.c | 161 +++++++++++++++++++++ 4 files changed, 205 insertions(+) create mode 100644 doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt create mode 100644 drivers/pinctrl/broadcom/pinctrl-bcm6838.c diff --git a/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt b/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt new file mode 100644 index 0000000000..2034f05993 --- /dev/null +++ b/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt @@ -0,0 +1,35 @@ +* broadcom bcm6838 pinctrl + +Required properties for the pinctrl driver: +- compatible: "brcm,bcm6838-pinctrl" +- regmap: specify the gpio test port syscon +- brcm,pins-count: the number of pin +- brcm,functions-count: the number of function + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Example: + + gpio_test_port: syscon@14e00294 { + compatible = "syscon"; + reg = <0x14e00294 0x1c>; + }; + + pinctrl: pinctrl { + compatible = "brcm,bcm6838-pinctrl"; + regmap = <&gpio_test_port>; + brcm,pins-count = <74>; + brcm,functions-count = <8>; + + usb0: usb0 { + usb0_pwrflt { + pins = "69"; + function = "1"; + }; + usb0_pwron { + pins = "70"; + function = "1"; + }; + }; + }; diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig index 4056782213..b01b725583 100644 --- a/drivers/pinctrl/broadcom/Kconfig +++ b/drivers/pinctrl/broadcom/Kconfig @@ -5,3 +5,11 @@ config PINCTRL_BCM283X help Support pin multiplexing and pin configuration control on Broadcom's 283x family of SoCs. + +config PINCTRL_BCM6838 + depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL + default y + bool "Broadcom 6838 family pin control driver" + help + Support pin multiplexing and pin configuration control on + Broadcom's 6838 family of SoCs. diff --git a/drivers/pinctrl/broadcom/Makefile b/drivers/pinctrl/broadcom/Makefile index 99c7c23583..f94f3ce7c9 100644 --- a/drivers/pinctrl/broadcom/Makefile +++ b/drivers/pinctrl/broadcom/Makefile @@ -5,3 +5,4 @@ # https://spdx.org/licenses obj-$(CONFIG_PINCTRL_BCM283X) += pinctrl-bcm283x.o +obj-$(CONFIG_PINCTRL_BCM6838) += pinctrl-bcm6838.o diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm6838.c b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c new file mode 100644 index 0000000000..48c0b6b374 --- /dev/null +++ b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include + +#define BCM6838_CMD_LOAD_MUX 0x21 + +#define BCM6838_FUNC_OFFS 12 +#define BCM6838_FUNC_MASK (0x37 << BCM6838_FUNC_OFFS) +#define BCM6838_PIN_OFFS 0 +#define BCM6838_PIN_MASK (0xfff << BCM6838_PIN_OFFS) + +#define BCM6838_MAX_PIN_NAME_LEN 8 +static char bcm6838_pin_name[BCM6838_MAX_PIN_NAME_LEN]; + +#define BCM6838_MAX_FUNC_NAME_LEN 8 +static char bcm6838_func_name[BCM6838_MAX_FUNC_NAME_LEN]; + +struct bcm6838_test_port_hw { + unsigned long port_blk_data1; + unsigned long port_blk_data2; + unsigned long port_command; +}; + +static const struct bcm6838_test_port_hw bcm6838_hw = { + .port_blk_data1 = 0x10, + .port_blk_data2 = 0x14, + .port_command = 0x18 +}; + +struct bcm6838_pinctrl_priv { + const struct bcm6838_test_port_hw *hw; + struct regmap *regmap; + u32 pins_count; + u32 functions_count; +}; + +int bcm6838_pinctrl_get_pins_count(struct udevice *dev) +{ + struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->pins_count; +} + +const char *bcm6838_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(bcm6838_pin_name, BCM6838_MAX_PIN_NAME_LEN, "%u", selector); + return bcm6838_pin_name; +} + +int bcm6838_pinctrl_get_functions_count(struct udevice *dev) +{ + struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->functions_count; +} + +const char *bcm6838_pinctrl_get_function_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(bcm6838_func_name, BCM6838_MAX_FUNC_NAME_LEN, "%u", selector); + return bcm6838_func_name; +} + +int bcm6838_pinctrl_pinmux_set(struct udevice *dev, + unsigned int pin_selector, + unsigned int func_selector) +{ + struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev); + const struct bcm6838_test_port_hw *hw = priv->hw; + unsigned int data; + + regmap_write(priv->regmap, hw->port_blk_data1, 0); + data = (func_selector << BCM6838_FUNC_OFFS) & BCM6838_FUNC_MASK; + data |= (pin_selector << BCM6838_PIN_OFFS) & BCM6838_PIN_MASK; + regmap_write(priv->regmap, hw->port_blk_data2, data); + regmap_write(priv->regmap, hw->port_command, BCM6838_CMD_LOAD_MUX); + + return 0; +} + +int bcm6838_pinctrl_probe(struct udevice *dev) +{ + struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev); + const struct bcm6838_test_port_hw *hw = + (const struct bcm6838_test_port_hw *)dev_get_driver_data(dev); + int err; + u32 phandle; + ofnode node; + + err = ofnode_read_u32(dev_ofnode(dev), "regmap", &phandle); + if (err) { + dev_err(dev, "%s: unable to read regmap\n", __func__); + goto out; + } + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) { + dev_err(dev, "%s: unable to find node\n", __func__); + err = -EINVAL; + goto out; + } + + priv->regmap = syscon_node_to_regmap(node); + if (!priv->regmap) { + dev_err(dev, "%s: unable to find regmap\n", __func__); + err = -ENODEV; + goto out; + } + + err = ofnode_read_u32(dev_ofnode(dev), "brcm,pins-count", + &priv->pins_count); + if (err) { + dev_err(dev, "%s: unable to read brcm,pins-count\n", + __func__); + goto out; + } + + err = ofnode_read_u32(dev_ofnode(dev), "brcm,functions-count", + &priv->functions_count); + if (err) { + dev_err(dev, "%s: unable to read brcm,functions-count\n", + __func__); + goto out; + } + + priv->hw = hw; + + out: + return err; +} + +const struct pinctrl_ops bcm6838_pinctrl_ops = { + .set_state = pinctrl_generic_set_state, + .get_pins_count = bcm6838_pinctrl_get_pins_count, + .get_pin_name = bcm6838_pinctrl_get_pin_name, + .get_functions_count = bcm6838_pinctrl_get_functions_count, + .get_function_name = bcm6838_pinctrl_get_function_name, + .pinmux_set = bcm6838_pinctrl_pinmux_set, +}; + +static const struct udevice_id bcm6838_pinctrl_match[] = { + { + .compatible = "brcm,bcm6838-pinctrl", + .data = (ulong)&bcm6838_hw, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6838_pinctrl) = { + .name = "bcm6838_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = bcm6838_pinctrl_match, + .ops = &bcm6838_pinctrl_ops, + .priv_auto_alloc_size = sizeof(struct bcm6838_pinctrl_priv), + .probe = bcm6838_pinctrl_probe, +}; -- cgit From e98a260eb5aac0b647391766700bb5af52be53da Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 13 Aug 2018 14:23:08 +0200 Subject: dt: bcm6838: add pinctrl Add pinctrl node and related syscon node for broadcom bcm6838 SoC. Signed-off-by: Philippe Reynes --- arch/mips/dts/brcm,bcm6838.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi index d365d0f2ce..1018f9ee49 100644 --- a/arch/mips/dts/brcm,bcm6838.dtsi +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -55,6 +55,18 @@ u-boot,dm-pre-reloc; }; + gpio_test_port: syscon@14e00294 { + compatible = "syscon"; + reg = <0x14e00294 0x1c>; + }; + + pinctrl: pinctrl { + compatible = "brcm,bcm6838-pinctrl"; + regmap = <&gpio_test_port>; + brcm,pins-count = <74>; + brcm,functions-count = <8>; + }; + uart0: serial@14e00500 { compatible = "brcm,bcm6345-uart"; reg = <0x14e00500 0x18>; -- cgit From 32f3179ae602971beb29e9d1981e77f9006a2c53 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 13 Aug 2018 14:23:09 +0200 Subject: bcm968380gerg: enable pinctrl Signed-off-by: Philippe Reynes --- configs/bcm968380gerg_ram_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 4943c8af3b..8b2b3183e6 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -39,6 +39,7 @@ CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y +CONFIG_PINCTRL=y CONFIG_POWER_DOMAIN=y CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_DM_RESET=y -- cgit From d1c3d8bdfa41a7002bc9c9c0fe8cf7b41d573c0e Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Sep 2018 19:18:44 +0200 Subject: MIPS: start.S: make boot config at offset 0x10 configurable Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck --- README | 5 ----- arch/mips/Kconfig | 23 +++++++++++++++++++++++ arch/mips/cpu/start.S | 21 +++++---------------- scripts/config_whitelist.txt | 1 - 4 files changed, 28 insertions(+), 22 deletions(-) diff --git a/README b/README index 09822a317d..21d1f8a007 100644 --- a/README +++ b/README @@ -542,11 +542,6 @@ The following options need to be configured: CONF_CM_CACHABLE_CUW CONF_CM_CACHABLE_ACCELERATED - CONFIG_SYS_XWAY_EBU_BOOTCFG - - Special option for Lantiq XWAY SoCs for booting from NOR flash. - See also arch/mips/cpu/mips32/start.S. - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6e5e0ffe65..f71597f6da 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -28,6 +28,7 @@ config TARGET_MALTA select DM_SERIAL select DYNAMIC_IO_PORT_BASE select MIPS_CM + select MIPS_INSERT_BOOT_CONFIG select MIPS_L1_CACHE_SHIFT_6 select MIPS_L2_CACHE select OF_CONTROL @@ -390,6 +391,28 @@ config MIPS_CM wish U-Boot to configure it or make use of it to retrieve system information such as cache configuration. +config MIPS_INSERT_BOOT_CONFIG + bool + default n + help + Enable this to insert some board-specific boot configuration in + the U-Boot binary at offset 0x10. + +config MIPS_BOOT_CONFIG_WORD0 + hex + depends on MIPS_INSERT_BOOT_CONFIG + default 0x420 if TARGET_MALTA + default 0x0 + help + Value which is inserted as boot config word 0. + +config MIPS_BOOT_CONFIG_WORD1 + hex + depends on MIPS_INSERT_BOOT_CONFIG + default 0x0 + help + Value which is inserted as boot config word 1. + endif endmenu diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6ca0916c06..1d21b2324a 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -84,25 +84,14 @@ ENTRY(_start) b reset mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing -#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) +#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* - * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to - * access external NOR flashes. If the board boots from NOR flash the - * internal BootROM does a blind read at address 0xB0000010 to read the - * initial configuration for that EBU in order to access the flash - * device with correct parameters. This config option is board-specific. + * Store some board-specific boot configuration. This is used by some + * MIPS systems like Malta. */ .org 0x10 - .word CONFIG_SYS_XWAY_EBU_BOOTCFG - .word 0x0 -#endif -#if defined(CONFIG_MALTA) - /* - * Linux expects the Board ID here. - */ - .org 0x10 - .word 0x00000420 # 0x420 (Malta Board with CoreLV) - .word 0x00000000 + .word CONFIG_MIPS_BOOT_CONFIG_WORD0 + .word CONFIG_MIPS_BOOT_CONFIG_WORD1 #endif #if defined(CONFIG_ROM_EXCEPTION_VECTORS) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 94953d8738..15c1cc08b7 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4421,7 +4421,6 @@ CONFIG_SYS_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR CONFIG_SYS_XIMG_LEN -CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -- cgit From 2f85c2be21dfee1e8ac1f8fb9759be7108233e85 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Sep 2018 19:02:03 +0200 Subject: MIPS: cache: reimplement dcache_[status, enable, disable] Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: Daniel Schwierzeck --- arch/mips/lib/cache.c | 20 ++++++++++++++++++++ arch/mips/lib/cache_init.S | 46 ---------------------------------------------- 2 files changed, 20 insertions(+), 46 deletions(-) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 1d14fc487e..d56fd1e0f4 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -175,3 +175,23 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) /* ensure cache ops complete before any further memory accesses */ sync(); } + +int dcache_status(void) +{ + unsigned int cca = read_c0_config() & CONF_CM_CMASK; + return cca != CONF_CM_UNCACHED; +} + +void dcache_enable(void) +{ + puts("Not supported!\n"); +} + +void dcache_disable(void) +{ + /* change CCA to uncached */ + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + + /* ensure the pipeline doesn't contain now-invalid instructions */ + instruction_hazard_barrier(); +} diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index b209f23f0a..395bfffdb8 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -423,49 +423,3 @@ return: sync jr ra END(mips_cache_reset) - -/* - * dcache_status - get cache status - * - * RETURNS: 0 - cache disabled; 1 - cache enabled - * - */ -LEAF(dcache_status) - mfc0 t0, CP0_CONFIG - li t1, CONF_CM_UNCACHED - andi t0, t0, CONF_CM_CMASK - move v0, zero - beq t0, t1, 2f - li v0, 1 -2: jr ra - END(dcache_status) - -/* - * dcache_disable - disable cache - * - * RETURNS: N/A - * - */ -LEAF(dcache_disable) - mfc0 t0, CP0_CONFIG - li t1, -8 - and t0, t0, t1 - ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_disable) - -/* - * dcache_enable - enable cache - * - * RETURNS: N/A - * - */ -LEAF(dcache_enable) - mfc0 t0, CP0_CONFIG - ori t0, CONF_CM_CMASK - xori t0, CONF_CM_CMASK - ori t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_enable) -- cgit From b838586086af3278bcaead3720c7a18813cf4619 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Sep 2018 19:02:04 +0200 Subject: MIPS: cache: optimise changing of k0 CCA mode Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before changing the CCA mode. Jump back to KSEG0 afterwards. Signed-off-by: Daniel Schwierzeck --- arch/mips/lib/cache_init.S | 54 +++++++++++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 395bfffdb8..4e956031b3 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -84,6 +84,7 @@ 10: .set pop .endm + /* * mips_cache_reset - low level initialisation of the primary caches * @@ -319,19 +320,21 @@ l1_init: PTR_LI t0, INDEX_BASE cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I #endif - - /* Enable use of the I-cache by setting Config.K0 */ sync - mfc0 t0, CP0_CONFIG - li t1, CONFIG_SYS_MIPS_CACHE_MODE -#if __mips_isa_rev >= 2 - ins t0, t1, 0, 3 -#else - ori t0, t0, CONF_CM_CMASK - xori t0, t0, CONF_CM_CMASK + + /* + * Enable use of the I-cache by setting Config.K0. The code for this + * must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this. + * Jump back to KSEG0 after caches are enabled and insert an + * instruction hazard barrier. + */ + PTR_LA t0, change_k0_cca + li t1, CPHYSADDR(~0) + and t0, t0, t1 + PTR_LI t1, CKSEG1 or t0, t0, t1 -#endif - mtc0 t0, CP0_CONFIG + li a0, CONFIG_SYS_MIPS_CACHE_MODE + jalr.hb t0 /* * then initialize D-cache. @@ -391,16 +394,9 @@ l2_unbypass: beqz t0, 2f /* Change Config.K0 to a coherent CCA */ - mfc0 t0, CP0_CONFIG - li t1, CONF_CM_CACHABLE_COW -#if __mips_isa_rev >= 2 - ins t0, t1, 0, 3 -#else - ori t0, t0, CONF_CM_CMASK - xori t0, t0, CONF_CM_CMASK - or t0, t0, t1 -#endif - mtc0 t0, CP0_CONFIG + PTR_LA t0, change_k0_cca + li a0, CONF_CM_CACHABLE_COW + jalr t0 /* * Join the coherent domain such that the caches of this core are kept @@ -421,5 +417,19 @@ l2_unbypass: return: /* Ensure all cache operations complete before returning */ sync - jr ra + jr R_RETURN END(mips_cache_reset) + +LEAF(change_k0_cca) + mfc0 t0, CP0_CONFIG +#if __mips_isa_rev >= 2 + ins t0, a0, 0, 3 +#else + xor a0, a0, t0 + andi a0, a0, CONF_CM_CMASK + xor a0, a0, t0 +#endif + mtc0 a0, CP0_CONFIG + + jr.hb ra + END(change_k0_cca) -- cgit From 5ef337a0371e2b2c7905e7e20a38b6bfc80bb708 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Sep 2018 19:02:05 +0200 Subject: MIPS: cache: make index base address configurable The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck --- arch/mips/Kconfig | 12 ++++++++++++ arch/mips/lib/cache_init.S | 18 ++++++++---------- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f71597f6da..30fb9bff74 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -219,6 +219,18 @@ config MIPS_CM_BASE the GCRs occupy a region of the physical address space which is otherwise unused, or at minimum that software doesn't need to access. +config MIPS_CACHE_INDEX_BASE + hex "Index base address for cache initialisation" + default 0x80000000 if CPU_MIPS32 + default 0xffffffff80000000 if CPU_MIPS64 + help + This is the base address for a memory block, which is used for + initialising the cache lines. This is also the base address of a memory + block which is used for loading and filling cache lines when + SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. + Normally this is CKSEG0. If the MIPS system needs to move this block + to some SRAM or ScratchPad RAM, adapt this option accordingly. + endmenu menu "OS boot interface" diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 4e956031b3..5616ee6dfd 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -18,8 +18,6 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif -#define INDEX_BASE CKSEG0 - .macro f_fill64 dst, offset, val LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) @@ -256,7 +254,7 @@ l2_probe_done: /* * Now clear that much memory starting from zero. */ - PTR_LI a0, CKSEG1 + PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) PTR_ADDU a1, a0, v0 2: PTR_ADDIU a0, 64 f_fill64 a0, -64, zero @@ -272,7 +270,7 @@ l2_probe_done: bnez R_L2_BYPASSED, l1_init l2_init: - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) PTR_ADDU t1, t0, R_L2_SIZE 1: cache INDEX_STORE_TAG_SD, 0(t0) PTR_ADDU t0, t0, R_L2_LINE @@ -308,16 +306,16 @@ l1_init: * Initialize the I-cache first, */ blez R_IC_SIZE, 1f - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) PTR_ADDU t1, t0, R_IC_SIZE /* clear tag to invalidate */ cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* fill once, so data field parity is correct */ - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) cache_loop t0, t1, R_IC_LINE, FILL /* invalidate again - prudent but not strictly neccessary */ - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I #endif sync @@ -340,18 +338,18 @@ l1_init: * then initialize D-cache. */ 1: blez R_DC_SIZE, 3f - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) PTR_ADDU t1, t0, R_DC_SIZE /* clear all tags */ cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* load from each line (in cached space) */ - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) 2: LONG_L zero, 0(t0) PTR_ADDU t0, R_DC_LINE bne t0, t1, 2b /* clear all tags */ - PTR_LI t0, INDEX_BASE + PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D #endif 3: -- cgit From 46203baf665c6bab72bd5945a37d9a7e0a77699a Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 7 Sep 2018 19:02:06 +0200 Subject: MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck --- README | 14 -------------- arch/mips/lib/cache_init.S | 6 +----- include/configs/imgtec_xilfpga.h | 3 --- include/configs/pic32mzdask.h | 3 --- scripts/config_whitelist.txt | 1 - 5 files changed, 1 insertion(+), 26 deletions(-) diff --git a/README b/README index 21d1f8a007..f7ed7eaae1 100644 --- a/README +++ b/README @@ -528,20 +528,6 @@ The following options need to be configured: pointer. This is needed for the temporary stack before relocation. - CONFIG_SYS_MIPS_CACHE_MODE - - Cache operation mode for the MIPS CPU. - See also arch/mips/include/asm/mipsregs.h. - Possible values are: - CONF_CM_CACHABLE_NO_WA - CONF_CM_CACHABLE_WA - CONF_CM_UNCACHED - CONF_CM_CACHABLE_NONCOHERENT - CONF_CM_CACHABLE_CE - CONF_CM_CACHABLE_COW - CONF_CM_CACHABLE_CUW - CONF_CM_CACHABLE_ACCELERATED - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 5616ee6dfd..cfad1d9c8a 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -14,10 +14,6 @@ #include #include -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - .macro f_fill64 dst, offset, val LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) @@ -331,7 +327,7 @@ l1_init: and t0, t0, t1 PTR_LI t1, CKSEG1 or t0, t0, t1 - li a0, CONFIG_SYS_MIPS_CACHE_MODE + li a0, CONF_CM_CACHABLE_NONCOHERENT jalr.hb t0 /* diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index 29b23fa40e..8e2d72323d 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -19,9 +19,6 @@ /* CPU Timer rate */ #define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 -/* Cache Configuration */ -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT - /*---------------------------------------------------------------------- * Memory Layout */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 374957737d..d3ab5575ee 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -16,9 +16,6 @@ /* CPU Timer rate */ #define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 -/* Cache Configuration */ -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT - /*---------------------------------------------------------------------- * Memory Layout */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 15c1cc08b7..e058a06e8f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3424,7 +3424,6 @@ CONFIG_SYS_MEM_TOP_HIDE CONFIG_SYS_MFD CONFIG_SYS_MHZ CONFIG_SYS_MII_MODE -CONFIG_SYS_MIPS_CACHE_MODE CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR -- cgit From 503f6f759c6b637e360f86b086557f8ca6398164 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2018 15:27:29 +0200 Subject: mips: Add arch/mips/include/asm/atomic.h This is needed for the UBIFS support. The file is a copy of arch/xtensa/include/asm/atomic.h Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/include/asm/atomic.h | 54 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 arch/mips/include/asm/atomic.h diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h new file mode 100644 index 0000000000..7551bf6e6c --- /dev/null +++ b/arch/mips/include/asm/atomic.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + */ + +#ifndef _MIPS_ATOMIC_H +#define _MIPS_ATOMIC_H + +#include + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v, i) ((v)->counter = (i)) + +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + ++v->counter; + local_irq_restore(flags); +} + +static inline void atomic_dec(atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + --v->counter; + local_irq_restore(flags); +} + +#endif -- cgit From 4c835a607bd5adf88a726c0f636b00dd31e50237 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 5 Sep 2018 15:12:35 +0200 Subject: mips: Add basic MediaTek MT7620/88 support This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git The mt7628a.dtsi file is imported from Linux v4.17. Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/Kconfig | 16 ++ arch/mips/Makefile | 1 + arch/mips/dts/mt7628a.dtsi | 135 ++++++++++++++ arch/mips/mach-mt7620/Kconfig | 113 ++++++++++++ arch/mips/mach-mt7620/Makefile | 8 + arch/mips/mach-mt7620/cpu.c | 69 ++++++++ arch/mips/mach-mt7620/ddr_calibrate.c | 308 ++++++++++++++++++++++++++++++++ arch/mips/mach-mt7620/lowlevel_init.S | 322 ++++++++++++++++++++++++++++++++++ arch/mips/mach-mt7620/mt76xx.h | 32 ++++ 9 files changed, 1004 insertions(+) create mode 100644 arch/mips/dts/mt7628a.dtsi create mode 100644 arch/mips/mach-mt7620/Kconfig create mode 100644 arch/mips/mach-mt7620/Makefile create mode 100644 arch/mips/mach-mt7620/cpu.c create mode 100644 arch/mips/mach-mt7620/ddr_calibrate.c create mode 100644 arch/mips/mach-mt7620/lowlevel_init.S create mode 100644 arch/mips/mach-mt7620/mt76xx.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 30fb9bff74..10b55c914e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -69,6 +69,21 @@ config ARCH_BMIPS select SYSRESET imply CMD_DM +config ARCH_MT7620 + bool "Support MT7620/7688 SoCs" + imply CMD_DM + select DISPLAY_CPUINFO + select DM + select DM_SERIAL + imply DM_SPI + imply DM_SPI_FLASH + select MIPS_TUNE_24KC + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -121,6 +136,7 @@ source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" +source "arch/mips/mach-mt7620/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a36f5f1fb6..802244a06e 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -14,6 +14,7 @@ libs-y += arch/mips/lib/ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 +machine-$(CONFIG_ARCH_MT7620) += mt7620 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi new file mode 100644 index 0000000000..d00f528e1f --- /dev/null +++ b/arch/mips/dts/mt7628a.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,mt7628a-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mti,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + resetc: reset-controller { + compatible = "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@10000000 { + compatible = "palmbus", "simple-bus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc: system-controller@0 { + compatible = "ralink,mt7620a-sysc", "syscon"; + reg = <0x0 0x100>; + }; + + intc: interrupt-controller@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&resetc 9>; + reset-names = "intc"; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + ralink,intc-registers = <0x9c 0xa0 + 0x6c 0xa4 + 0x80 0x78>; + }; + + memory-controller@300 { + compatible = "ralink,mt7620a-memc"; + reg = <0x300 0x100>; + }; + + spi0: spi@b00 { + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x40>; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: uartlite@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + resets = <&resetc 12>; + reset-names = "uart0"; + + interrupt-parent = <&intc>; + interrupts = <20>; + + reg-shift = <2>; + }; + + uart1: uart1@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + resets = <&resetc 19>; + reset-names = "uart1"; + + interrupt-parent = <&intc>; + interrupts = <21>; + + reg-shift = <2>; + }; + + uart2: uart2@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + + resets = <&resetc 20>; + reset-names = "uart2"; + + interrupt-parent = <&intc>; + interrupts = <22>; + + reg-shift = <2>; + }; + }; + + usb_phy: usb-phy@10120000 { + compatible = "mediatek,mt7628-usbphy"; + reg = <0x10120000 0x1000>; + + #phy-cells = <0>; + + ralink,sysctl = <&sysc>; + resets = <&resetc 22 &resetc 25>; + reset-names = "host", "device"; + }; + + ehci@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x1000>; + + phys = <&usb_phy>; + phy-names = "usb"; + + interrupt-parent = <&intc>; + interrupts = <18>; + }; +}; diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig new file mode 100644 index 0000000000..396fbd0141 --- /dev/null +++ b/arch/mips/mach-mt7620/Kconfig @@ -0,0 +1,113 @@ +menu "MediaTek MIPS platforms" + depends on ARCH_MT7620 + +config SYS_MALLOC_F_LEN + default 0x1000 + +config SYS_SOC + default "mt7620" if SOC_MT7620 + +choice + prompt "MediaTek MIPS SoC select" + +config SOC_MT7620 + bool "MT7620/8" + select MIPS_L1_CACHE_SHIFT_5 + help + This supports MediaTek MIPS MT7620 family. + +endchoice + +choice + prompt "Board select" + +endchoice + +choice + prompt "Boot mode" + +config BOOT_RAM + bool "RAM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a RAM address. It can be used + for booting from CFE via TFTP using an ELF image, but it can also be + booted from RAM by other bootloaders using a BIN image. + +config BOOT_ROM + bool "ROM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a ROM address. It can be + used as main bootloader image which is programmed onto the onboard + flash storage (SPI NOR). + +endchoice + +choice + prompt "DDR2 size" + +config ONBOARD_DDR2_SIZE_256MBIT + bool "256MBit (32MByte) total size" + depends on BOOT_ROM + help + Use 256MBit (32MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_512MBIT + bool "512MBit (64MByte) total size" + depends on BOOT_ROM + help + Use 512MBit (64MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_1024MBIT + bool "1024MBit (128MByte) total size" + depends on BOOT_ROM + help + Use 1024MBit (128MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_2048MBIT + bool "2048MBit (256MByte) total size" + depends on BOOT_ROM + help + Use 2048MBit (256MByte) of DDR total size + +endchoice + +choice + prompt "DDR2 chip width" + +config ONBOARD_DDR2_CHIP_WIDTH_8BIT + bool "8bit DDR chip width" + depends on BOOT_ROM + help + Use DDR chips with 8bit width + +config ONBOARD_DDR2_CHIP_WIDTH_16BIT + bool "16bit DDR chip width" + depends on BOOT_ROM + help + Use DDR chips with 16bit width + +endchoice + +choice + prompt "DDR2 bus width" + +config ONBOARD_DDR2_BUS_WIDTH_16BIT + bool "16bit DDR bus width" + depends on BOOT_ROM + help + Use 16bit DDR bus width + +config ONBOARD_DDR2_BUS_WIDTH_32BIT + bool "32bit DDR bus width" + depends on BOOT_ROM + help + Use 32bit DDR bus width + +endchoice + +config SUPPORTS_BOOT_RAM + bool + +endmenu diff --git a/arch/mips/mach-mt7620/Makefile b/arch/mips/mach-mt7620/Makefile new file mode 100644 index 0000000000..1f3e65e8a5 --- /dev/null +++ b/arch/mips/mach-mt7620/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += cpu.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +obj-y += ddr_calibrate.o +obj-y += lowlevel_init.o +endif diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c new file mode 100644 index 0000000000..457f09f32c --- /dev/null +++ b/arch/mips/mach-mt7620/cpu.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include +#include +#include +#include +#include +#include "mt76xx.h" + +#define STR_LEN 6 + +#ifdef CONFIG_BOOT_ROM +int mach_cpu_init(void) +{ + ddr_calibrate(); + + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M); + + return 0; +} + +int print_cpuinfo(void) +{ + static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)", + "PLL (4-Byte SPI Addr)", + "XTAL (3-Byte SPI Addr)", + "XTAL (4-Byte SPI Addr)" }; + const void *blob = gd->fdt_blob; + void __iomem *sysc_base; + char buf[STR_LEN + 1]; + fdt_addr_t base; + fdt_size_t size; + char *str; + int node; + u32 val; + + /* Get system controller base address */ + node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", + 0, &size, true); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + sysc_base = ioremap_nocache(base, size); + + str = (char *)sysc_base + MT76XX_CHIPID_OFFS; + snprintf(buf, STR_LEN + 1, "%s", str); + val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS); + printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf, + (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0)); + + val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1; + printf("Boot from %s\n", boot_str[val]); + + return 0; +} diff --git a/arch/mips/mach-mt7620/ddr_calibrate.c b/arch/mips/mach-mt7620/ddr_calibrate.c new file mode 100644 index 0000000000..75763c4528 --- /dev/null +++ b/arch/mips/mach-mt7620/ddr_calibrate.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + * + * Most functions in this file are copied from the MediaTek U-Boot + * repository. Without any documentation, it was impossible to really + * implement this differently. So its mostly a cleaned-up version of + * the original code, with only support for the MT7628 / MT7688 SoC. + */ + +#include +#include +#include +#include +#include "mt76xx.h" + +#define NUM_OF_CACHELINE 128 +#define MIN_START 6 +#define MIN_FINE_START 0xf +#define MAX_START 7 +#define MAX_FINE_START 0x0 + +#define CPU_FRAC_DIV 1 + +#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) +#define DRAM_BUTTOM 0x02000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) +#define DRAM_BUTTOM 0x04000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) +#define DRAM_BUTTOM 0x08000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) +#define DRAM_BUTTOM 0x10000000 +#endif + +static inline void cal_memcpy(void *src, void *dst, u32 size) +{ + u8 *psrc = (u8 *)src; + u8 *pdst = (u8 *)dst; + int i; + + for (i = 0; i < size; i++, psrc++, pdst++) + *pdst = *psrc; +} + +static inline void cal_memset(void *src, u8 pat, u32 size) +{ + u8 *psrc = (u8 *)src; + int i; + + for (i = 0; i < size; i++, psrc++) + *psrc = pat; +} + +#define pref_op(hint, addr) \ + __asm__ __volatile__( \ + ".set push\n" \ + ".set noreorder\n" \ + "pref %0, %1\n" \ + ".set pop\n" \ + : \ + : "i" (hint), "R" (*(u8 *)(addr))) + +static inline void cal_patgen(u32 start_addr, u32 size, u32 bias) +{ + u32 *addr = (u32 *)start_addr; + int i; + + for (i = 0; i < size; i++) + addr[i] = start_addr + i + bias; +} + +static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs, + u32 offs, u32 pat, u32 val) +{ + u32 nc_addr; + u32 *c_addr; + int i; + + for (nc_addr = 0xa0000000; + nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32); + nc_addr += (DRAM_BUTTOM >> 6) + offs) { + writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64); + wmb(); /* Make sure store if finished */ + + c_addr = (u32 *)(nc_addr & 0xdfffffff); + cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32); + cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat); + + if (dqs > 0) + writel(0x00000074 | + (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) | + (((k == 0) ? val : test_dqs) << 8), + (void *)MT76XX_MEMCTRL_BASE + 0x64); + else + writel(0x00007400 | + (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) | + (((k == 0) ? val : test_dqs) << 0), + (void *)MT76XX_MEMCTRL_BASE + 0x64); + wmb(); /* Make sure store if finished */ + + invalidate_dcache_range((u32)c_addr, + (u32)c_addr + + NUM_OF_CACHELINE * 32); + wmb(); /* Make sure store if finished */ + + for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { + if (i % 8 == 0) + pref_op(0, &c_addr[i]); + } + + for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { + if (c_addr[i] != nc_addr + i + pat) + return -1; + } + } + + return 0; +} + +void ddr_calibrate(void) +{ + u32 min_coarse_dqs[2]; + u32 max_coarse_dqs[2]; + u32 min_fine_dqs[2]; + u32 max_fine_dqs[2]; + u32 coarse_dqs[2]; + u32 fine_dqs[2]; + int reg = 0, ddr_cfg2_reg; + int flag; + int i, k; + int dqs = 0; + u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll; + u32 val; + u32 fdiv = 0, frac = 0; + + /* Setup clock to run at full speed */ + val = readl((void *)MT76XX_DYN_CFG0_REG); + fdiv = (u32)((val >> 8) & 0x0F); + if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10) + frac = val & 0x0f; + else + frac = CPU_FRAC_DIV; + + while (frac < fdiv) { + val = readl((void *)MT76XX_DYN_CFG0_REG); + fdiv = (val >> 8) & 0x0f; + fdiv--; + val &= ~(0x0f << 8); + val |= (fdiv << 8); + writel(val, (void *)MT76XX_DYN_CFG0_REG); + udelay(500); + val = readl((void *)MT76XX_DYN_CFG0_REG); + fdiv = (val >> 8) & 0x0f; + } + + clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48); + clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48, + (0x3 << 28) | (0x3 << 26)); + + min_coarse_dqs[0] = MIN_START; + min_coarse_dqs[1] = MIN_START; + min_fine_dqs[0] = MIN_FINE_START; + min_fine_dqs[1] = MIN_FINE_START; + max_coarse_dqs[0] = MAX_START; + max_coarse_dqs[1] = MAX_START; + max_fine_dqs[0] = MAX_FINE_START; + max_fine_dqs[1] = MAX_FINE_START; + dqs = 0; + + /* Add by KP, DQS MIN boundary */ + reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20); + coarse_dqs_dll = (reg & 0xf00) >> 8; + fine_dqs_dll = (reg & 0xf0) >> 4; + if (coarse_dqs_dll <= 8) + min_coarse_dqs_bnd = 8 - coarse_dqs_dll; + else + min_coarse_dqs_bnd = 0; + + if (fine_dqs_dll <= 8) + min_fine_dqs_bnd = 8 - fine_dqs_dll; + else + min_fine_dqs_bnd = 0; + /* DQS MIN boundary */ + +DQS_CAL: + + for (k = 0; k < 2; k++) { + u32 test_dqs; + + if (k == 0) + test_dqs = MAX_START; + else + test_dqs = MAX_FINE_START; + + do { + flag = test_loop(k, dqs, test_dqs, max_coarse_dqs, + 0x400, 0x3, 0xf); + if (flag == -1) + break; + + test_dqs++; + } while (test_dqs <= 0xf); + + if (k == 0) { + max_coarse_dqs[dqs] = test_dqs; + } else { + test_dqs--; + + if (test_dqs == MAX_FINE_START - 1) { + max_coarse_dqs[dqs]--; + max_fine_dqs[dqs] = 0xf; + } else { + max_fine_dqs[dqs] = test_dqs; + } + } + } + + for (k = 0; k < 2; k++) { + u32 test_dqs; + + if (k == 0) + test_dqs = MIN_START; + else + test_dqs = MIN_FINE_START; + + do { + flag = test_loop(k, dqs, test_dqs, min_coarse_dqs, + 0x480, 0x1, 0x0); + if (k == 0) { + if (flag == -1 || + test_dqs == min_coarse_dqs_bnd) + break; + + test_dqs--; + + if (test_dqs < min_coarse_dqs_bnd) + break; + } else { + if (flag == -1) { + test_dqs++; + break; + } else if (test_dqs == min_fine_dqs_bnd) { + break; + } + + test_dqs--; + + if (test_dqs < min_fine_dqs_bnd) + break; + } + } while (test_dqs >= 0); + + if (k == 0) { + min_coarse_dqs[dqs] = test_dqs; + } else { + if (test_dqs == MIN_FINE_START + 1) { + min_coarse_dqs[dqs]++; + min_fine_dqs[dqs] = 0x0; + } else { + min_fine_dqs[dqs] = test_dqs; + } + } + } + + if (dqs == 0) { + dqs = 1; + goto DQS_CAL; + } + + for (i = 0; i < 2; i++) { + u32 temp; + + coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1; + temp = + (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) + + ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1); + if (temp >= 0x10) { + coarse_dqs[i]++; + fine_dqs[i] = (temp - 0x10) + 0x8; + } else { + fine_dqs[i] = temp; + } + } + reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) | + (coarse_dqs[0] << 4) | fine_dqs[0]; + + clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64); + writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48); + setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + + for (i = 0; i < 2; i++) + debug("[%02X%02X%02X%02X]", min_coarse_dqs[i], + min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]); + debug("\nDDR Calibration DQS reg = %08X\n", reg); +} diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S new file mode 100644 index 0000000000..1a50f160fe --- /dev/null +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2018 Stefan Roese + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include +#include +#include +#include +#include +#include "mt76xx.h" + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define DELAY_USEC(us) ((us) / 100) + +#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16) +#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12) + +#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) +#define DDR_CFG1_SIZE_VAL 0x222e2323 +#define DDR_CFG4_SIZE_VAL 7 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) +#define DDR_CFG1_SIZE_VAL 0x22322323 +#define DDR_CFG4_SIZE_VAL 9 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) +#define DDR_CFG1_SIZE_VAL 0x22362323 +#define DDR_CFG4_SIZE_VAL 9 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) +#define DDR_CFG1_SIZE_VAL 0x223a2323 +#define DDR_CFG4_SIZE_VAL 9 +#endif + +#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT) +#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16) +#endif +#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT) +#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16) +#endif + +#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT) +#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12) +#endif +#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT) +#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12) +#endif + + .set noreorder + +LEAF(lowlevel_init) + + /* Load base addresses as physical addresses for later usage */ + li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE) + li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE) + li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE) + + /* polling CPLL is ready */ + li t1, DELAY_USEC(1000000) + la t5, MT76XX_ROM_STATUS_REG +1: + lw t2, 0(t5) + andi t2, t2, 0x1 + bnez t2, CPLL_READY + subu t1, t1, 1 + bgtz t1, 1b + nop + la t0, MT76XX_CLKCFG0_REG + lw t3, 0(t0) + ori t3, t3, 0x1 + sw t3, 0(t0) + b CPLL_DONE + nop +CPLL_READY: + la t0, MT76XX_CLKCFG0_REG + lw t1, 0(t0) + li t2, ~0x0c + and t1, t1, t2 + ori t1, t1, 0xc + sw t1, 0(t0) + la t0, MT76XX_DYN_CFG0_REG + lw t3, 0(t0) + li t5, ~((0x0f << 8) | (0x0f << 0)) + and t3, t3, t5 + li t5, (10 << 8) | (1 << 0) + or t3, t3, t5 + sw t3, 0(t0) + la t0, MT76XX_CLKCFG0_REG + lw t3, 0(t0) + li t4, ~0x0F + and t3, t3, t4 + ori t3, t3, 0xc + sw t3, 0(t0) + lw t3, 0(t0) + ori t3, t3, 0x08 + sw t3, 0(t0) + +CPLL_DONE: + /* + * SDR and DDR initialization: delay 200us + */ + li t0, DELAY_USEC(200 + 40) + li t1, 0x1 +1: + sub t0, t0, t1 + bnez t0, 1b + nop + + /* set DRAM IO PAD for MT7628IC */ + /* DDR LDO Enable */ + lw t4, 0x100(s2) + li t2, BIT(31) + or t4, t4, t2 + sw t4, 0x100(s2) + lw t4, 0x10c(s2) + j LDO_1P8V + nop +LDO_1P8V: + li t2, ~BIT(6) + and t4, t4, t2 + sw t4, 0x10c(s2) + j DDRLDO_SOFT_START +LDO_2P5V: + /* suppose external DDR1 LDO 2.5V */ + li t2, BIT(6) + or t4, t4, t2 + sw t4, 0x10c(s2) + +DDRLDO_SOFT_START: + lw t2, 0x10c(s2) + li t3, BIT(16) + or t2, t2, t3 + sw t2, 0x10c(s2) + li t3, DELAY_USEC(250*50) +LDO_DELAY: + subu t3, t3, 1 + bnez t3, LDO_DELAY + nop + + lw t2, 0x10c(s2) + li t3, BIT(18) + or t2, t2, t3 + sw t2, 0x10c(s2) + +SET_RG_BUCK_FPWM: + lw t2, 0x104(s2) + ori t2, t2, BIT(10) + sw t2, 0x104(s2) + +DDR_PAD_CFG: + /* clean CLK PAD */ + lw t2, 0x704(s2) + li t8, 0xfffff0f0 + and t2, t2, t8 + /* clean CMD PAD */ + lw t3, 0x70c(s2) + li t8, 0xfffff0f0 + and t3, t3, t8 + /* clean DQ IPAD */ + lw t4, 0x710(s2) + li t8, 0xfffff8ff + and t4, t4, t8 + /* clean DQ OPAD */ + lw t5, 0x714(s2) + li t8, 0xfffff0f0 + and t5, t5, t8 + /* clean DQS IPAD */ + lw t6, 0x718(s2) + li t8, 0xfffff8ff + and t6, t6, t8 + /* clean DQS OPAD */ + lw t7, 0x71c(s2) + li t8, 0xfffff0f0 + and t7, t7, t8 + + lw t9, 0xc(s0) + srl t9, t9, 16 + andi t9, t9, 0x1 + bnez t9, MT7628_AN_DDR1_PAD +MT7628_KN_PAD: + li t8, 0x00000303 + or t2, t2, t8 + or t3, t3, t8 + or t5, t5, t8 + or t7, t7, t8 + li t8, 0x00000000 + or t4, t4, t8 + or t6, t6, t8 + j SET_PAD_CFG +MT7628_AN_DDR1_PAD: + lw t1, 0x10(s0) + andi t1, t1, 0x1 + beqz t1, MT7628_AN_DDR2_PAD + li t8, 0x00000c0c + or t2, t2, t8 + li t8, 0x00000202 + or t3, t3, t8 + li t8, 0x00000707 + or t5, t5, t8 + li t8, 0x00000c0c + or t7, t7, t8 + li t8, 0x00000000 + or t4, t4, t8 + or t6, t6, t8 + j SET_PAD_CFG +MT7628_AN_DDR2_PAD: + li t8, 0x00000c0c + or t2, t2, t8 + li t8, 0x00000202 + or t3, t3, t8 + li t8, 0x00000404 + or t5, t5, t8 + li t8, 0x00000c0c + or t7, t7, t8 + li t8, 0x00000000 /* ODT off */ + or t4, t4, t8 + or t6, t6, t8 + +SET_PAD_CFG: + sw t2, 0x704(s2) + sw t3, 0x70c(s2) + sw t4, 0x710(s2) + sw t5, 0x714(s2) + sw t6, 0x718(s2) + sw t7, 0x71c(s2) + + /* + * DDR initialization: reset pin to 0 + */ + lw t2, 0x34(s0) + and t2, ~BIT(10) + sw t2, 0x34(s0) + nop + + /* + * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready) + */ +DDR_READY: + li t1, DDR_CFG1_REG + lw t0, 0(t1) + nop + and t2, t0, BIT(21) + beqz t2, DDR_READY + nop + + /* + * DDR initialization + * + * Only DDR2 supported right now. DDR2 support can be added, once + * boards using it will get added to mainline U-Boot. + */ + li t1, DDR_CFG2_REG + lw t0, 0(t1) + nop + and t0, ~BIT(30) + and t0, ~(7 << 4) + or t0, (4 << 4) + or t0, BIT(30) + or t0, BIT(11) + sw t0, 0(t1) + nop + + li t1, DDR_CFG3_REG + lw t2, 0(t1) + /* Disable ODT; reference board ok, ev board fail */ + and t2, ~BIT(6) + or t2, BIT(2) + li t0, DDR_CFG4_REG + lw t1, 0(t0) + li t2, ~(0x01f | 0x0f0) + and t1, t1, t2 + ori t1, t1, DDR_CFG4_SIZE_VAL + sw t1, 0(t0) + nop + + /* + * DDR initialization: config size and width on reg DDR_CFG1 + */ + li t6, DDR_CFG1_SIZE_VAL + + and t6, ~DDR_CFG1_CHIP_WIDTH_MASK + or t6, DDR_CFG1_CHIP_WIDTH_VAL + + /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */ + and t6, ~DDR_CFG1_BUS_WIDTH_MASK + or t6, DDR_CFG1_BUS_WIDTH_VAL + + li t5, DDR_CFG1_REG + sw t6, 0(t5) + nop + + /* + * DDR: enable self auto refresh for power saving + * enable it by default for both RAM and ROM version (for CoC) + */ + lw t1, 0x14(s1) + nop + and t1, 0xff000000 + or t1, 0x01 + sw t1, 0x14(s1) + nop + lw t1, 0x10(s1) + nop + or t1, 0x10 + sw t1, 0x10(s1) + nop + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-mt7620/mt76xx.h b/arch/mips/mach-mt7620/mt76xx.h new file mode 100644 index 0000000000..17473ea8f1 --- /dev/null +++ b/arch/mips/mach-mt7620/mt76xx.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __MT76XX_H +#define __MT76XX_H + +#define MT76XX_SYSCTL_BASE 0x10000000 + +#define MT76XX_CHIPID_OFFS 0x00 +#define MT76XX_CHIP_REV_ID_OFFS 0x0c +#define MT76XX_SYSCFG0_OFFS 0x10 + +#define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300) +#define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000) + +#define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028) +#define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c) +#define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440) + +#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) +#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48) +#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c) +#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50) + +#ifndef __ASSEMBLY__ +/* Prototypes */ +void ddr_calibrate(void); +#endif + +#endif -- cgit From b02f76a83541fe9fe3a2918039b26fc133699c17 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2018 15:27:30 +0200 Subject: mips: Add LinkIt Smart 7688 support The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI NOR). This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck --- arch/mips/dts/linkit-smart-7688.dts | 46 ++++++++++++++++++++++++++ arch/mips/mach-mt7620/Kconfig | 13 ++++++++ board/seeed/linkit-smart-7688/Kconfig | 12 +++++++ board/seeed/linkit-smart-7688/MAINTAINERS | 8 +++++ board/seeed/linkit-smart-7688/Makefile | 3 ++ board/seeed/linkit-smart-7688/board.c | 26 +++++++++++++++ configs/linkit-smart-7688-ram_defconfig | 51 ++++++++++++++++++++++++++++ configs/linkit-smart-7688_defconfig | 55 +++++++++++++++++++++++++++++++ include/configs/linkit-smart-7688.h | 51 ++++++++++++++++++++++++++++ 9 files changed, 265 insertions(+) create mode 100644 arch/mips/dts/linkit-smart-7688.dts create mode 100644 board/seeed/linkit-smart-7688/Kconfig create mode 100644 board/seeed/linkit-smart-7688/MAINTAINERS create mode 100644 board/seeed/linkit-smart-7688/Makefile create mode 100644 board/seeed/linkit-smart-7688/board.c create mode 100644 configs/linkit-smart-7688-ram_defconfig create mode 100644 configs/linkit-smart-7688_defconfig create mode 100644 include/configs/linkit-smart-7688.h diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts new file mode 100644 index 0000000000..df4bf907c6 --- /dev/null +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc"; + model = "LinkIt-Smart-7688"; + + aliases { + serial0 = &uart2; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + stdout-path = &uart2; + }; +}; + +&uart2 { + status = "okay"; + clock-frequency = <40000000>; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig index 396fbd0141..ef1211d172 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mt7620/Kconfig @@ -21,6 +21,17 @@ endchoice choice prompt "Board select" +config BOARD_LINKIT_SMART_7688 + bool "LinkIt Smart 7688" + depends on SOC_MT7620 + select SUPPORTS_BOOT_RAM + help + Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM + and 32 MiB of flash (SPI). + Between its different peripherals there's an integrated switch with 4 + ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and + a MT7688 (PCIe). + endchoice choice @@ -110,4 +121,6 @@ endchoice config SUPPORTS_BOOT_RAM bool +source "board/seeed/linkit-smart-7688/Kconfig" + endmenu diff --git a/board/seeed/linkit-smart-7688/Kconfig b/board/seeed/linkit-smart-7688/Kconfig new file mode 100644 index 0000000000..a9d63285c3 --- /dev/null +++ b/board/seeed/linkit-smart-7688/Kconfig @@ -0,0 +1,12 @@ +if BOARD_LINKIT_SMART_7688 + +config SYS_BOARD + default "linkit-smart-7688" + +config SYS_VENDOR + default "seeed" + +config SYS_CONFIG_NAME + default "linkit-smart-7688" + +endif diff --git a/board/seeed/linkit-smart-7688/MAINTAINERS b/board/seeed/linkit-smart-7688/MAINTAINERS new file mode 100644 index 0000000000..c3bbad4231 --- /dev/null +++ b/board/seeed/linkit-smart-7688/MAINTAINERS @@ -0,0 +1,8 @@ +LINKIT_SMART_7688 BOARD +M: Stefan Roese +S: Maintained +F: board/seeed/linkit-smart-7688 +F: include/configs/linkit-smart-7688.h +F: configs/linkit-smart-7688_defconfig +F: configs/linkit-smart-7688_ram_defconfig +F: arch/mips/dts/linkit-smart-7688.dts diff --git a/board/seeed/linkit-smart-7688/Makefile b/board/seeed/linkit-smart-7688/Makefile new file mode 100644 index 0000000000..70cd7a8e56 --- /dev/null +++ b/board/seeed/linkit-smart-7688/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o diff --git a/board/seeed/linkit-smart-7688/board.c b/board/seeed/linkit-smart-7688/board.c new file mode 100644 index 0000000000..a28abc00b8 --- /dev/null +++ b/board/seeed/linkit-smart-7688/board.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include + +#define MT76XX_GPIO1_MODE 0xb0000060 + +void board_debug_uart_init(void) +{ + /* Select UART2 mode instead of GPIO mode (default) */ + clrbits_le32((void __iomem *)MT76XX_GPIO1_MODE, GENMASK(27, 26)); +} + +int board_early_init_f(void) +{ + /* + * The pin muxing of UART2 also needs to be done, if debug uart + * is not enabled. So we need to call this function here as well. + */ + board_debug_uart_init(); + + return 0; +} diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig new file mode 100644 index 0000000000..77cd1c1575 --- /dev/null +++ b/configs/linkit-smart-7688-ram_defconfig @@ -0,0 +1,51 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_MT7620=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig new file mode 100644 index 0000000000..62cdda1e0a --- /dev/null +++ b/configs/linkit-smart-7688_defconfig @@ -0,0 +1,55 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9c000000 +CONFIG_ARCH_MT7620=y +CONFIG_BOOT_ROM=y +CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y +CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h new file mode 100644 index 0000000000..78efa23279 --- /dev/null +++ b/include/configs/linkit-smart-7688.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __CONFIG_LINKIT_SMART_7688_H +#define __CONFIG_LINKIT_SMART_7688_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#ifdef CONFIG_BOOT_RAM +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE (16 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) + +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +#endif /* __CONFIG_LINKIT_SMART_7688_H */ -- cgit From 88dc40991494951015978b381bc37899fd9971d4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2018 15:27:31 +0200 Subject: mips: Add Gardena Smart-Gateway board support The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage. This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck --- arch/mips/dts/gardena-smart-gateway-mt7688.dts | 54 ++++++++++++++++++++ arch/mips/mach-mt7620/Kconfig | 9 ++++ board/gardena/smart-gateway-mt7688/Kconfig | 12 +++++ board/gardena/smart-gateway-mt7688/MAINTAINERS | 8 +++ board/gardena/smart-gateway-mt7688/Makefile | 3 ++ board/gardena/smart-gateway-mt7688/board.c | 17 +++++++ configs/gardena-smart-gateway-mt7688-ram_defconfig | 55 ++++++++++++++++++++ configs/gardena-smart-gateway-mt7688_defconfig | 58 ++++++++++++++++++++++ include/configs/gardena-smart-gateway-mt7688.h | 55 ++++++++++++++++++++ 9 files changed, 271 insertions(+) create mode 100644 arch/mips/dts/gardena-smart-gateway-mt7688.dts create mode 100644 board/gardena/smart-gateway-mt7688/Kconfig create mode 100644 board/gardena/smart-gateway-mt7688/MAINTAINERS create mode 100644 board/gardena/smart-gateway-mt7688/Makefile create mode 100644 board/gardena/smart-gateway-mt7688/board.c create mode 100644 configs/gardena-smart-gateway-mt7688-ram_defconfig create mode 100644 configs/gardena-smart-gateway-mt7688_defconfig create mode 100644 include/configs/gardena-smart-gateway-mt7688.h diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts new file mode 100644 index 0000000000..ee99c3d17c --- /dev/null +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc"; + model = "Gardena smart-Gateway-MT7688"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + stdout-path = &uart0; + }; +}; + +&uart0 { + status = "okay"; + clock-frequency = <40000000>; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + + spi-nand@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <40000000>; + reg = <1>; + }; +}; diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig index ef1211d172..13a7bd2cc0 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mt7620/Kconfig @@ -21,6 +21,14 @@ endchoice choice prompt "Board select" +config BOARD_GARDENA_SMART_GATEWAY_MT7688 + bool "Gardena Smart Gateway" + depends on SOC_MT7620 + select SUPPORTS_BOOT_RAM + help + Gardena Smart Gateway boards have a MT7688 SoC with 128 MiB of RAM + and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. + config BOARD_LINKIT_SMART_7688 bool "LinkIt Smart 7688" depends on SOC_MT7620 @@ -121,6 +129,7 @@ endchoice config SUPPORTS_BOOT_RAM bool +source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" endmenu diff --git a/board/gardena/smart-gateway-mt7688/Kconfig b/board/gardena/smart-gateway-mt7688/Kconfig new file mode 100644 index 0000000000..3653f8aadb --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/Kconfig @@ -0,0 +1,12 @@ +if BOARD_GARDENA_SMART_GATEWAY_MT7688 + +config SYS_BOARD + default "smart-gateway-mt7688" + +config SYS_VENDOR + default "gardena" + +config SYS_CONFIG_NAME + default "gardena-smart-gateway-mt7688" + +endif diff --git a/board/gardena/smart-gateway-mt7688/MAINTAINERS b/board/gardena/smart-gateway-mt7688/MAINTAINERS new file mode 100644 index 0000000000..bbb491c1ce --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/MAINTAINERS @@ -0,0 +1,8 @@ +GARDENA_SMART_GATEWAY_MT7688 BOARD +M: Stefan Roese +S: Maintained +F: board/gardena/smart-gateway-mt7688 +F: include/configs/gardena-smart-gateway-mt7688.h +F: configs/gardena-smart-gateway-mt7688_defconfig +F: configs/gardena-smart-gateway-mt7688-ram_defconfig +F: arch/mips/dts/gardena-smart-gateway-mt7688.dts diff --git a/board/gardena/smart-gateway-mt7688/Makefile b/board/gardena/smart-gateway-mt7688/Makefile new file mode 100644 index 0000000000..70cd7a8e56 --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c new file mode 100644 index 0000000000..5ff546f505 --- /dev/null +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#include +#include + +int board_early_init_f(void) +{ + /* + * Nothing to be done here for this board (no UART setup etc) + * right now. We might need some pin muxing, so lets keep this + * function for now. + */ + return 0; +} diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig new file mode 100644 index 0000000000..0e2f158518 --- /dev/null +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -0,0 +1,55 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_MT7620=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)" +CONFIG_CMD_UBI=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MTD=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig new file mode 100644 index 0000000000..1213227758 --- /dev/null +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -0,0 +1,58 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9c000000 +CONFIG_ARCH_MT7620=y +CONFIG_BOOT_ROM=y +CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y +CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)" +CONFIG_CMD_UBI=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MTD=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=57600 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_SYSRESET_SYSCON=y diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h new file mode 100644 index 0000000000..0184147068 --- /dev/null +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H +#define __CONFIG_GARDENA_SMART_GATEWAY_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#ifdef CONFIG_BOOT_RAM +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ +#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ -- cgit From 41f6e6eb644751678fb3c0b92b74e7f058c7cb89 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2018 15:27:32 +0200 Subject: mips: mt76xx: Add sysreset support This patch adds the necessary sysreset DT node and enables the required drivers via Kconfig. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/Kconfig | 1 + arch/mips/dts/mt7628a.dtsi | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 10b55c914e..071dea04ec 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -83,6 +83,7 @@ config ARCH_MT7620 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN + select SYSRESET config MACH_PIC32 bool "Support Microchip PIC32" diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index d00f528e1f..d525f019fe 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -41,6 +41,13 @@ reg = <0x0 0x100>; }; + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysc>; + offset = <0x34>; + mask = <0x1>; + }; + intc: interrupt-controller@200 { compatible = "ralink,rt2880-intc"; reg = <0x200 0x100>; -- cgit From fdd1a9ff781cda82696f8971e540e475fd1e9933 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2018 15:27:33 +0200 Subject: mips: mt7628a.dtsi: Add SPI clock-frequency property This patch adds the clock-frequency property to the SPI controller DT node. It will be used by the SPI driver to calculate the baud rate. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/dts/mt7628a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index d525f019fe..c14259b170 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -76,6 +76,8 @@ reg = <0xb00 0x40>; #address-cells = <1>; #size-cells = <0>; + + clock-frequency = <200000000>; }; uart0: uartlite@c00 { -- cgit