From c82216803d50014814350e6adce695ea699e6999 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Sun, 15 Dec 2019 22:29:39 +0000 Subject: env: another attempt at fixing SPL build failures I'm also seeing the build failure that commit 7d4776545b env: solve compilation error in SPL tried to fix, namely that the reference to env_flags_validate from env_htab cannot be satisfied when flags.o is not built in. However, that commit got reverted by d90fc9c3de Revert "env: solve compilation error in SPL" Necessary, but not sufficient conditions to see this are CONFIG_SPL=y (obviously) CONFIG_SPL_ENV_SUPPORT=n (so flags.o does not get compiled) CONFIG_SPL_LIBCOMMON_SUPPORT=y (so env/built-in.o is part of the SPL link) Now, these are satisfied for e.g. imx6q_logic_defconfig. But that builds just fine, and spl/u-boot-spl.map lists .data.env_htab among the discarded (garbage collected) sections. Yet, on our mpc8309-derived board, we do see the build failure, so perhaps the linker works a bit differently on ppc than on ARM, or there's yet some other configuration option needed to observe the break. This is another attempt at solving it, which also cleans up env/Makefile a bit: Introduce a def_bool y symbol CONFIG_ENV_SUPPORT which complements CONFIG_(SPL/TPL)_SUPPORT. Then use CONFIG_$(SPL_TPL_)ENV_SUPPORT to decide whether to include the five basic env/*.o files. For attr.o, flags.o and callback.o, this shouldn't change anything. Also, common.o and env.o still get unconditionally built for U-boot proper. But for TPL/SPL, those two are only included if CONFIG_(SPL/TPL)_SUPPORT is set. Having that symbol should also allow simplifying conditionals such as #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) found in drivers/reset/reset-socfpga.c to just CONFIG_IS_ENABLED(ENV_SUPPORT). Signed-off-by: Rasmus Villemoes --- env/Kconfig | 3 +++ env/Makefile | 13 +++++-------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/env/Kconfig b/env/Kconfig index ed12609f6a..4661082f0e 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -1,5 +1,8 @@ menu "Environment" +config ENV_SUPPORT + def_bool y + config ENV_IS_NOWHERE bool "Environment is not stored" default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ diff --git a/env/Makefile b/env/Makefile index 90144d6caf..e2a165b8f1 100644 --- a/env/Makefile +++ b/env/Makefile @@ -3,12 +3,13 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y += common.o env.o +obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += common.o +obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += env.o +obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += attr.o +obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o +obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += callback.o ifndef CONFIG_SPL_BUILD -obj-y += attr.o -obj-y += callback.o -obj-y += flags.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o extra-$(CONFIG_ENV_IS_EMBEDDED) += embedded.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += embedded.o @@ -19,10 +20,6 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += onenand.o obj-$(CONFIG_ENV_IS_IN_SATA) += sata.o obj-$(CONFIG_ENV_IS_IN_REMOTE) += remote.o obj-$(CONFIG_ENV_IS_IN_UBI) += ubi.o -else -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += attr.o -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += callback.o endif obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE) += nowhere.o -- cgit From 057b613990d1665d1d2936655a1aca1962126800 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sat, 4 Jan 2020 18:45:15 +0100 Subject: timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij --- drivers/timer/Kconfig | 9 +++ drivers/timer/Makefile | 1 + drivers/timer/nomadik-mtu-timer.c | 114 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 drivers/timer/nomadik-mtu-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 96cc49273f..637024445c 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -127,6 +127,15 @@ config X86_TSC_TIMER_EARLY_FREQ hardware ways, nor got from device tree at the time when device tree is not available yet. +config NOMADIK_MTU_TIMER + bool "Nomadik MTU Timer" + depends on TIMER + help + Enables support for the Nomadik Multi Timer Unit (MTU), + used in ST-Ericsson Ux500 SoCs. + The MTU provides 4 decrementing free-running timers. + At the moment, only the first timer is used by the driver. + config OMAP_TIMER bool "Omap timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fa35bea6c5..c22ffebcde 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o +obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o diff --git a/drivers/timer/nomadik-mtu-timer.c b/drivers/timer/nomadik-mtu-timer.c new file mode 100644 index 0000000000..8648f1f1df --- /dev/null +++ b/drivers/timer/nomadik-mtu-timer.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Stephan Gerhold + * + * Based on arch/arm/cpu/armv7/u8500/timer.c: + * Copyright (C) 2010 Linaro Limited + * John Rigby + * + * Based on Linux kernel source and internal ST-Ericsson U-Boot source: + * Copyright (C) 2009 Alessandro Rubini + * Copyright (C) 2010 ST-Ericsson + * Copyright (C) 2010 Linus Walleij for ST-Ericsson + */ + +#include +#include +#include +#include + +#define MTU_NUM_TIMERS 4 + +/* The timers */ +struct nomadik_mtu_timer_regs { + u32 lr; /* Load register */ + u32 cv; /* Current value */ + u32 cr; /* Control register */ + u32 bglr; /* Background load register */ +}; + +/* The MTU that contains the timers */ +struct nomadik_mtu_regs { + u32 imsc; /* Interrupt mask set/clear */ + u32 ris; /* Raw interrupt status */ + u32 mis; /* Masked interrupt status */ + u32 icr; /* Interrupt clear register */ + + struct nomadik_mtu_timer_regs timers[MTU_NUM_TIMERS]; +}; + +/* Bits for the control register */ +#define MTU_CR_ONESHOT BIT(0) /* if 0 = wraps reloading from BGLR */ +#define MTU_CR_32BITS BIT(1) /* if 0 = 16-bit counter */ + +#define MTU_CR_PRESCALE_SHIFT 2 +#define MTU_CR_PRESCALE_1 (0 << MTU_CR_PRESCALE_SHIFT) +#define MTU_CR_PRESCALE_16 (1 << MTU_CR_PRESCALE_SHIFT) +#define MTU_CR_PRESCALE_256 (2 << MTU_CR_PRESCALE_SHIFT) + +#define MTU_CR_PERIODIC BIT(6) /* if 0 = free-running */ +#define MTU_CR_ENABLE BIT(7) + +struct nomadik_mtu_priv { + struct nomadik_mtu_timer_regs *timer; +}; + +static int nomadik_mtu_get_count(struct udevice *dev, u64 *count) +{ + struct nomadik_mtu_priv *priv = dev_get_priv(dev); + + /* Decrementing counter: invert the value */ + *count = timer_conv_64(~readl(&priv->timer->cv)); + + return 0; +} + +static int nomadik_mtu_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct nomadik_mtu_priv *priv = dev_get_priv(dev); + struct nomadik_mtu_regs *mtu; + fdt_addr_t addr; + u32 prescale; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + mtu = (struct nomadik_mtu_regs *)addr; + priv->timer = mtu->timers; /* Use first timer */ + + if (!uc_priv->clock_rate) + return -EINVAL; + + /* Use divide-by-16 counter if tick rate is more than 32 MHz */ + if (uc_priv->clock_rate > 32000000) { + uc_priv->clock_rate /= 16; + prescale = MTU_CR_PRESCALE_16; + } else { + prescale = MTU_CR_PRESCALE_1; + } + + /* Configure a free-running, auto-wrap counter with selected prescale */ + writel(MTU_CR_ENABLE | prescale | MTU_CR_32BITS, &priv->timer->cr); + + return 0; +} + +static const struct timer_ops nomadik_mtu_ops = { + .get_count = nomadik_mtu_get_count, +}; + +static const struct udevice_id nomadik_mtu_ids[] = { + { .compatible = "st,nomadik-mtu" }, + {} +}; + +U_BOOT_DRIVER(nomadik_mtu) = { + .name = "nomadik_mtu", + .id = UCLASS_TIMER, + .of_match = nomadik_mtu_ids, + .priv_auto_alloc_size = sizeof(struct nomadik_mtu_priv), + .probe = nomadik_mtu_probe, + .ops = &nomadik_mtu_ops, +}; -- cgit From f13dc8cbd9df5c4eab4f0c6481ba403dbe4e8729 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sat, 4 Jan 2020 18:45:16 +0100 Subject: arm: dts: Import device tree for ST-Ericsson Ux500 from https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/ tag "ux500-armsoc-v5.6-2" commit 224bf0fe7292 ("ARM: dts: ux500: samsung-golden: Add Bluetooth") (queued for merge in Linux 5.6) Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij --- arch/arm/dts/ste-ab8500.dtsi | 328 ++++++++ arch/arm/dts/ste-ab8505.dtsi | 275 +++++++ arch/arm/dts/ste-dbx5x0.dtsi | 1144 ++++++++++++++++++++++++++++ include/dt-bindings/arm/ux500_pm_domains.h | 15 + include/dt-bindings/clock/ste-ab8500.h | 12 + include/dt-bindings/mfd/dbx500-prcmu.h | 84 ++ 6 files changed, 1858 insertions(+) create mode 100644 arch/arm/dts/ste-ab8500.dtsi create mode 100644 arch/arm/dts/ste-ab8505.dtsi create mode 100644 arch/arm/dts/ste-dbx5x0.dtsi create mode 100644 include/dt-bindings/arm/ux500_pm_domains.h create mode 100644 include/dt-bindings/clock/ste-ab8500.h create mode 100644 include/dt-bindings/mfd/dbx500-prcmu.h diff --git a/arch/arm/dts/ste-ab8500.dtsi b/arch/arm/dts/ste-ab8500.dtsi new file mode 100644 index 0000000000..14d4d8617d --- /dev/null +++ b/arch/arm/dts/ste-ab8500.dtsi @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include + +/ { + /* Essential housekeeping hardware monitors */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&gpadc 0x02>, /* Battery temperature */ + <&gpadc 0x03>, /* Main charger voltage */ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0a>, /* Main charger current */ + <&gpadc 0x0b>, /* USB charger current */ + <&gpadc 0x0c>, /* Backup battery voltage */ + <&gpadc 0x0d>, /* Die temperature */ + <&gpadc 0x12>; /* Crystal temperature */ + }; + + soc { + prcmu@80157000 { + ab8500 { + compatible = "stericsson,ab8500"; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + ab8500_clock: clock-controller { + compatible = "stericsson,ab8500-clk"; + #clock-cells = <1>; + }; + + ab8500_gpio: ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH + 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH + 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* GPADC channels */ + bat_ctrl: channel@01 { + reg = <0x01>; + }; + btemp_ball: channel@02 { + reg = <0x02>; + }; + main_charger_v: channel@03 { + reg = <0x03>; + }; + acc_detect1: channel@04 { + reg = <0x04>; + }; + acc_detect2: channel@05 { + reg = <0x05>; + }; + adc_aux1: channel@06 { + reg = <0x06>; + }; + adc_aux2: channel@07 { + reg = <0x07>; + }; + main_batt_v: channel@08 { + reg = <0x08>; + }; + vbus_v: channel@09 { + reg = <0x09>; + }; + main_charger_c: channel@0a { + reg = <0x0a>; + }; + usb_charger_c: channel@0b { + reg = <0x0b>; + }; + bk_bat_v: channel@0c { + reg = <0x0c>; + }; + die_temp: channel@0d { + reg = <0x0d>; + }; + usb_id: channel@0e { + reg = <0x0e>; + }; + xtal_temp: channel@12 { + reg = <0x12>; + }; + vbat_true_meas: channel@13 { + reg = <0x13>; + }; + bat_ctrl_and_ibat: channel@1c { + reg = <0x1c>; + }; + vbat_meas_and_ibat: channel@1d { + reg = <0x1d>; + }; + vbat_true_meas_and_ibat: channel@1e { + reg = <0x1e>; + }; + bat_temp_and_ibat: channel@1f { + reg = <0x1f>; + }; + }; + + ab8500_temp { + compatible = "stericsson,abx500-temp"; + io-channels = <&gpadc 0x06>, + <&gpadc 0x07>; + io-channel-name = "aux1", "aux2"; + }; + + ab8500_battery: ab8500_battery { + stericsson,battery-type = "LIPO"; + thermistor-on-batctrl; + }; + + ab8500_fg { + compatible = "stericsson,ab8500-fg"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x08>; + io-channel-name = "main_bat_v"; + }; + + ab8500_btemp { + compatible = "stericsson,ab8500-btemp"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; + io-channel-name = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + compatible = "stericsson,ab8500-charger"; + battery = <&ab8500_battery>; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + io-channels = <&gpadc 0x03>, + <&gpadc 0x0a>, + <&gpadc 0x09>, + <&gpadc 0x0b>; + io-channel-name = "main_charger_v", + "main_charger_c", + "vbus_v", + "usb_charger_c"; + }; + + ab8500_chargalg { + compatible = "stericsson,ab8500-chargalg"; + battery = <&ab8500_battery>; + }; + + ab8500_usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 90 IRQ_TYPE_LEVEL_HIGH + 96 IRQ_TYPE_LEVEL_HIGH + 14 IRQ_TYPE_LEVEL_HIGH + 15 IRQ_TYPE_LEVEL_HIGH + 79 IRQ_TYPE_LEVEL_HIGH + 74 IRQ_TYPE_LEVEL_HIGH + 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-poweron-key"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH + 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; + + codec: ab8500-codec { + compatible = "stericsson,ab8500-codec"; + + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + V-DMIC-supply = <&ab8500_ldo_dmic_reg>; + + clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; + clock-names = "audioclk"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + + ext_regulators: ab8500-ext-regulators { + compatible = "stericsson,ab8500-ext-regulator"; + + ab8500_ext1_reg: ab8500_ext1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext2_reg: ab8500_ext2 { + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext3_reg: ab8500_ext3 { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + }; + + ab8500-regulators { + compatible = "stericsson,ab8500-regulator"; + vin-supply = <&ab8500_ext3_reg>; + + // supplies to the display/camera + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + /* BUG: If turned off MMC will be affected. */ + regulator-always-on; + }; + + // supplies to the on-board eMMC + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for VAUX3; SDcard slots + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + }; + + // supply for tvout; gpadc; TVOUT LDO + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + }; + + // supply for v-anamic1 VAMIC1 LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + }; + + // supply for v-dmic; VDMIC LDO + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + }; + }; + }; + }; + + sound { + stericsson,audio-codec = <&codec>; + clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "sysclk", "ulpclk", "intclk"; + }; + + mcde@a0350000 { + vana-supply = <&ab8500_ldo_ana_reg>; + + dsi@a0351000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0352000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0353000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; + }; +}; diff --git a/arch/arm/dts/ste-ab8505.dtsi b/arch/arm/dts/ste-ab8505.dtsi new file mode 100644 index 0000000000..c72aa250bf --- /dev/null +++ b/arch/arm/dts/ste-ab8505.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include + +/ { + /* Essential housekeeping hardware monitors */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&gpadc 0x02>, /* Battery temperature */ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0b>, /* Charger current */ + <&gpadc 0x0c>; /* Backup battery voltage */ + }; + + soc { + prcmu@80157000 { + ab8505 { + compatible = "stericsson,ab8505"; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + ab8500_clock: clock-controller { + compatible = "stericsson,ab8500-clk"; + #clock-cells = <1>; + }; + + ab8505_gpio: ab8505-gpio { + compatible = "stericsson,ab8505-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH + 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH + 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_adc_reg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* GPADC channels */ + bat_ctrl: channel@01 { + reg = <0x01>; + }; + btemp_ball: channel@02 { + reg = <0x02>; + }; + acc_detect1: channel@04 { + reg = <0x04>; + }; + acc_detect2: channel@05 { + reg = <0x05>; + }; + adc_aux1: channel@06 { + reg = <0x06>; + }; + adc_aux2: channel@07 { + reg = <0x07>; + }; + main_batt_v: channel@08 { + reg = <0x08>; + }; + vbus_v: channel@09 { + reg = <0x09>; + }; + charger_c: channel@0b { + reg = <0x0b>; + }; + bk_bat_v: channel@0c { + reg = <0x0c>; + }; + usb_id: channel@0e { + reg = <0x0e>; + }; + }; + + ab8500_battery: ab8500_battery { + status = "disabled"; + thermistor-on-batctrl; + }; + + ab8500_fg { + status = "disabled"; + compatible = "stericsson,ab8500-fg"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x08>; + io-channel-name = "main_bat_v"; + }; + + ab8500_btemp { + status = "disabled"; + compatible = "stericsson,ab8500-btemp"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; + io-channel-name = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + status = "disabled"; + compatible = "stericsson,ab8500-charger"; + battery = <&ab8500_battery>; + vddadc-supply = <&ab8500_ldo_adc_reg>; + io-channels = <&gpadc 0x09>, + <&gpadc 0x0b>; + io-channel-name = "vbus_v", + "usb_charger_c"; + }; + + ab8500_chargalg { + status = "disabled"; + compatible = "stericsson,ab8500-chargalg"; + battery = <&ab8500_battery>; + }; + + ab8500_usb: ab8500_usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 90 IRQ_TYPE_LEVEL_HIGH + 96 IRQ_TYPE_LEVEL_HIGH + 14 IRQ_TYPE_LEVEL_HIGH + 15 IRQ_TYPE_LEVEL_HIGH + 79 IRQ_TYPE_LEVEL_HIGH + 74 IRQ_TYPE_LEVEL_HIGH + 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-poweron-key"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH + 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; + + codec: ab8500-codec { + compatible = "stericsson,ab8500-codec"; + + V-AUD-supply = <&ab8500_ldo_audio_reg>; + V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; + V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; + + clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; + clock-names = "audioclk"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + + ab8505-regulators { + compatible = "stericsson,ab8505-regulator"; + + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux4_reg: ab8500_ldo_aux4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5_reg: ab8500_ldo_aux5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + ab8500_ldo_aux6_reg: ab8500_ldo_aux6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + }; + + // supply for gpadc; ADC LDO + ab8500_ldo_adc_reg: ab8500_ldo_adc { + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + }; + + // supply for v-anamic1 VAMIC1 LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + }; + + // supply for v-aux8; VAUX8 LDO + ab8500_ldo_aux8_reg: ab8500_ldo_aux8 { + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + }; + }; + }; + }; + + sound { + stericsson,audio-codec = <&codec>; + clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "sysclk", "ulpclk", "intclk"; + }; + + mcde@a0350000 { + vana-supply = <&ab8500_ldo_ana_reg>; + + dsi@a0351000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0352000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + dsi@a0353000 { + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; + }; +}; diff --git a/arch/arm/dts/ste-dbx5x0.dtsi b/arch/arm/dts/ste-dbx5x0.dtsi new file mode 100644 index 0000000000..6671f74c9f --- /dev/null +++ b/arch/arm/dts/ste-dbx5x0.dtsi @@ -0,0 +1,1144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Linaro Ltd + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + /* This stablilizes the device enumeration */ + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "ste,dbx500-smp"; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + CPU0: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x300>; + clocks = <&prcmu_clk PRCMU_ARMSS>; + clock-names = "cpu"; + clock-latency = <20000>; + #cooling-cells = <2>; + }; + CPU1: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x301>; + }; + }; + + thermal-zones { + /* + * Thermal zone for the SoC, using the thermal sensor in the + * PRCMU for temperature and the cpufreq driver for passive + * cooling. + */ + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + /* + * This sensor fires interrupts to update the thermal + * zone, so no polling is needed. + */ + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu_alert: cpu-alert { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu-crit { + temperature = <85000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + trip = <&cpu_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <100>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500", "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + ptm@801ae000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801ae000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + ptm@801af000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801af000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + + funnel@801a6000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x801a6000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "atclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + tpiu@80190000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x80190000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + etb@801a4000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x801a4000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + scu@a0410000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + /* + * The backup RAM is used for retention during sleep + * and various things like spin tables + */ + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + pm_domains: pm_domains0 { + compatible = "stericsson,ux500-pm-domains"; + #power-domain-cells = <1>; + }; + + clocks { + compatible = "stericsson,u8500-clks"; + /* + * Registers for the CLKRST block on peripheral + * groups 1, 2, 3, 5, 6, + */ + reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, + <0x8000f000 0x1000>, <0xa03ff000 0x1000>, + <0xa03cf000 0x1000>; + + prcmu_clk: prcmu-clock { + #clock-cells = <1>; + }; + + prcc_pclk: prcc-periph-clock { + #clock-cells = <2>; + }; + + prcc_kclk: prcc-kernel-clock { + #clock-cells = <2>; + }; + + rtc_clk: rtc32k-clock { + #clock-cells = <0>; + }; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + }; + + mtu@a03c6000 { + /* Nomadik System Timer */ + compatible = "st,nomadik-mtu"; + reg = <0xa03c6000 0x1000>; + interrupts = ; + + clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; + clock-names = "timclk", "apb_pclk"; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = ; + + clocks = <&smp_twd_clk>; + }; + + watchdog@a0410620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xa0410620 0x20>; + interrupts = ; + clocks = <&smp_twd_clk>; + }; + + rtc@80154000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x80154000 0x1000>; + interrupts = ; + + clocks = <&rtc_clk>; + clock-names = "apb_pclk"; + }; + + gpio0: gpio@8012e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + clocks = <&prcc_pclk 1 9>; + }; + + gpio1: gpio@8012e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 5>; + clocks = <&prcc_pclk 1 9>; + }; + + gpio2: gpio@8000e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio3: gpio@8000e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e080 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <3>; + gpio-ranges = <&pinctrl 0 96 2>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio4: gpio@8000e100 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e100 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <4>; + gpio-ranges = <&pinctrl 0 128 32>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio5: gpio@8000e180 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e180 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <5>; + gpio-ranges = <&pinctrl 0 160 12>; + clocks = <&prcc_pclk 3 8>; + }; + + gpio6: gpio@8011e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <6>; + gpio-ranges = <&pinctrl 0 192 32>; + clocks = <&prcc_pclk 2 11>; + }; + + gpio7: gpio@8011e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e080 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <7>; + gpio-ranges = <&pinctrl 0 224 7>; + clocks = <&prcc_pclk 2 11>; + }; + + gpio8: gpio@a03fe000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0xa03fe000 0x80>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <8>; + gpio-ranges = <&pinctrl 0 256 12>; + clocks = <&prcc_pclk 5 1>; + }; + + pinctrl: pinctrl { + compatible = "stericsson,db8500-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, + <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, + <&gpio8>; + prcm = <&prcmu>; + }; + + usb_per5@a03e0000 { + compatible = "stericsson,db8500-musb"; + reg = <0xa03e0000 0x10000>; + interrupts = ; + interrupt-names = "mc"; + + dr_mode = "otg"; + + dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ + <&dma 38 0 0x0>, /* Logical - MemToDev */ + <&dma 37 0 0x2>, /* Logical - DevToMem */ + <&dma 37 0 0x0>, /* Logical - MemToDev */ + <&dma 36 0 0x2>, /* Logical - DevToMem */ + <&dma 36 0 0x0>, /* Logical - MemToDev */ + <&dma 19 0 0x2>, /* Logical - DevToMem */ + <&dma 19 0 0x0>, /* Logical - MemToDev */ + <&dma 18 0 0x2>, /* Logical - DevToMem */ + <&dma 18 0 0x0>, /* Logical - MemToDev */ + <&dma 17 0 0x2>, /* Logical - DevToMem */ + <&dma 17 0 0x0>, /* Logical - MemToDev */ + <&dma 16 0 0x2>, /* Logical - DevToMem */ + <&dma 16 0 0x0>, /* Logical - MemToDev */ + <&dma 39 0 0x2>, /* Logical - DevToMem */ + <&dma 39 0 0x0>; /* Logical - MemToDev */ + + dma-names = "iep_1_9", "oep_1_9", + "iep_2_10", "oep_2_10", + "iep_3_11", "oep_3_11", + "iep_4_12", "oep_4_12", + "iep_5_13", "oep_5_13", + "iep_6_14", "oep_6_14", + "iep_7_15", "oep_7_15", + "iep_8", "oep_8"; + + clocks = <&prcc_pclk 5 0>; + }; + + dma: dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", "stericsson,dma40"; + reg = <0x801C0000 0x1000 0x40010000 0x800>; + reg-names = "base", "lcpa"; + interrupts = ; + + #dma-cells = <3>; + memcpy-channels = <56 57 58 59 60>; + + clocks = <&prcmu_clk PRCMU_DMACLK>; + }; + + prcmu: prcmu@80157000 { + compatible = "stericsson,db8500-prcmu", "syscon"; + reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + prcmu-timer-4@80157450 { + compatible = "stericsson,db8500-prcmu-timer-4"; + reg = <0x80157450 0xC>; + }; + + thermal: thermal@801573c0 { + compatible = "stericsson,db8500-thermal"; + reg = <0x801573c0 0x40>; + interrupt-parent = <&prcmu>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; + #thermal-sensor-cells = <0>; + }; + + db8500-prcmu-regulators { + compatible = "stericsson,db8500-prcmu-regulator"; + + // DB8500_REGULATOR_VAPE + db8500_vape_reg: db8500_vape { + regulator-always-on; + }; + + // DB8500_REGULATOR_VARM + db8500_varm_reg: db8500_varm { + }; + + // DB8500_REGULATOR_VMODEM + db8500_vmodem_reg: db8500_vmodem { + }; + + // DB8500_REGULATOR_VPLL + db8500_vpll_reg: db8500_vpll { + }; + + // DB8500_REGULATOR_VSMPS1 + db8500_vsmps1_reg: db8500_vsmps1 { + }; + + // DB8500_REGULATOR_VSMPS2 + db8500_vsmps2_reg: db8500_vsmps2 { + }; + + // DB8500_REGULATOR_VSMPS3 + db8500_vsmps3_reg: db8500_vsmps3 { + }; + + // DB8500_REGULATOR_VRF1 + db8500_vrf1_reg: db8500_vrf1 { + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSP + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSPRET + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + }; + + // DB8500_REGULATOR_SWITCH_SVAPIPE + db8500_sva_pipe_reg: db8500_sva_pipe { + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSP + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSPRET + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + }; + + // DB8500_REGULATOR_SWITCH_SIAPIPE + db8500_sia_pipe_reg: db8500_sia_pipe { + }; + + // DB8500_REGULATOR_SWITCH_SGA + db8500_sga_reg: db8500_sga { + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_B2R2_MCDE + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12 + db8500_esram12_reg: db8500_esram12 { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12RET + db8500_esram12_ret_reg: db8500_esram12_ret { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34 + db8500_esram34_reg: db8500_esram34 { + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34RET + db8500_esram34_ret_reg: db8500_esram34_ret { + }; + }; + }; + + i2c0: i2c@80004000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80004000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c1: i2c@80122000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80122000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c2: i2c@80128000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80128000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c3: i2c@80110000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80110000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + i2c4: i2c@8012a000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x8012a000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + ssp0: spi@80002000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80002000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ + <&dma 8 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + ssp1: spi@80003000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80003000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ + <&dma 9 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi0: spi@8011a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8011a000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ + <&dma 0 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi1: spi@80112000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80112000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ + <&dma 35 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi2: spi@80111000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80111000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ + <&dma 33 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + spi3: spi@80129000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80129000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; + clock-names = "SSPCLK", "apb_pclk"; + dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ + <&dma 40 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + serial0: uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = ; + + dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ + <&dma 13 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; + clock-names = "uart", "apb_pclk"; + + status = "disabled"; + }; + + serial1: uart@80121000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80121000 0x1000>; + interrupts = ; + + dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ + <&dma 12 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; + clock-names = "uart", "apb_pclk"; + + status = "disabled"; + }; + + serial2: uart@80007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80007000 0x1000>; + interrupts = ; + + dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ + <&dma 11 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; + clock-names = "uart", "apb_pclk"; + + status = "disabled"; + }; + + sdi0_per1@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = ; + + dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ + <&dma 29 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi1_per2@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = ; + + dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ + <&dma 32 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi2_per3@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = ; + + dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ + <&dma 28 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi3_per2@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = ; + + dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ + <&dma 41 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi4_per2@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = ; + + dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ + <&dma 42 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sdi5_per3@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80008000 0x1000>; + interrupts = ; + + dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ + <&dma 43 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; + clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + + status = "disabled"; + }; + + sound { + compatible = "stericsson,snd-soc-mop500"; + stericsson,cpu-dai = <&msp1 &msp3>; + }; + + msp0: msp@80123000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80123000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + msp1: msp@80124000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80124000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + /* This DMA channel only exist on DB8500 v1 */ + dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "tx"; + + clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + // HDMI sound + msp2: msp@80117000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80117000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev + HighPrio - Fixed */ + dma-names = "rx", "tx"; + + clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + msp3: msp@80125000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80125000 0x1000>; + interrupts = ; + v-ape-supply = <&db8500_vape_reg>; + + /* This DMA channel only exist on DB8500 v2 */ + dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ + dma-names = "rx"; + + clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; + clock-names = "msp", "apb_pclk"; + + status = "disabled"; + }; + + external-bus@50000000 { + compatible = "simple-bus"; + reg = <0x50000000 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000000>; + status = "disabled"; + }; + + gpu@a0300000 { + /* + * This block is referred to as "Smart Graphics Adapter SGA500" + * in documentation but is in practice a pretty straight-forward + * MALI-400 GPU block. + */ + compatible = "stericsson,db8500-mali", "arm,mali-400"; + reg = <0xa0300000 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "combined"; + clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; + clock-names = "bus", "core"; + mali-supply = <&db8500_sga_reg>; + power-domains = <&pm_domains DOMAIN_VAPE>; + }; + + mcde@a0350000 { + compatible = "ste,mcde"; + reg = <0xa0350000 0x1000>; + interrupts = ; + epod-supply = <&db8500_b2r2_mcde_reg>; + clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ + <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ + <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ + clock-names = "mcde", "lcd", "hdmi"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dsi0: dsi@a0351000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0351000 0x1000>; + clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi1: dsi@a0352000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0352000 0x1000>; + clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; + clock-names = "hs", "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + dsi2: dsi@a0353000 { + compatible = "ste,mcde-dsi"; + reg = <0xa0353000 0x1000>; + /* This DSI port only has the Low Power / Energy Save clock */ + clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; + clock-names = "lp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cryp@a03cb000 { + compatible = "stericsson,ux500-cryp"; + reg = <0xa03cb000 0x1000>; + interrupts = ; + + v-ape-supply = <&db8500_vape_reg>; + clocks = <&prcc_pclk 6 1>; + }; + + hash@a03c2000 { + compatible = "stericsson,ux500-hash"; + reg = <0xa03c2000 0x1000>; + + v-ape-supply = <&db8500_vape_reg>; + clocks = <&prcc_pclk 6 2>; + }; + }; +}; diff --git a/include/dt-bindings/arm/ux500_pm_domains.h b/include/dt-bindings/arm/ux500_pm_domains.h new file mode 100644 index 0000000000..9bd764f0c9 --- /dev/null +++ b/include/dt-bindings/arm/ux500_pm_domains.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2014 Linaro Ltd. + * + * Author: Ulf Hansson + */ +#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H +#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H + +#define DOMAIN_VAPE 0 + +/* Number of PM domains. */ +#define NR_DOMAINS (DOMAIN_VAPE + 1) + +#endif diff --git a/include/dt-bindings/clock/ste-ab8500.h b/include/dt-bindings/clock/ste-ab8500.h new file mode 100644 index 0000000000..fb42dd0cab --- /dev/null +++ b/include/dt-bindings/clock/ste-ab8500.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __STE_CLK_AB8500_H__ +#define __STE_CLK_AB8500_H__ + +#define AB8500_SYSCLK_BUF2 0 +#define AB8500_SYSCLK_BUF3 1 +#define AB8500_SYSCLK_BUF4 2 +#define AB8500_SYSCLK_ULP 3 +#define AB8500_SYSCLK_INT 4 +#define AB8500_SYSCLK_AUDIO 5 + +#endif diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h new file mode 100644 index 0000000000..0404bcc47d --- /dev/null +++ b/include/dt-bindings/mfd/dbx500-prcmu.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the PRCMU bindings. + * + */ + +#ifndef _DT_BINDINGS_MFD_PRCMU_H +#define _DT_BINDINGS_MFD_PRCMU_H + +/* + * Clock identifiers. + */ +#define ARMCLK 0 +#define PRCMU_ACLK 1 +#define PRCMU_SVAMMCSPCLK 2 +#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ +#define PRCMU_SIACLK 3 +#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ +#define PRCMU_SGACLK 4 +#define PRCMU_UARTCLK 5 +#define PRCMU_MSP02CLK 6 +#define PRCMU_MSP1CLK 7 +#define PRCMU_I2CCLK 8 +#define PRCMU_SDMMCCLK 9 +#define PRCMU_SLIMCLK 10 +#define PRCMU_CAMCLK 10 /* DBx540 only. */ +#define PRCMU_PER1CLK 11 +#define PRCMU_PER2CLK 12 +#define PRCMU_PER3CLK 13 +#define PRCMU_PER5CLK 14 +#define PRCMU_PER6CLK 15 +#define PRCMU_PER7CLK 16 +#define PRCMU_LCDCLK 17 +#define PRCMU_BMLCLK 18 +#define PRCMU_HSITXCLK 19 +#define PRCMU_HSIRXCLK 20 +#define PRCMU_HDMICLK 21 +#define PRCMU_APEATCLK 22 +#define PRCMU_APETRACECLK 23 +#define PRCMU_MCDECLK 24 +#define PRCMU_IPI2CCLK 25 +#define PRCMU_DSIALTCLK 26 +#define PRCMU_DMACLK 27 +#define PRCMU_B2R2CLK 28 +#define PRCMU_TVCLK 29 +#define SPARE_UNIPROCLK 30 +#define PRCMU_SSPCLK 31 +#define PRCMU_RNGCLK 32 +#define PRCMU_UICCCLK 33 +#define PRCMU_G1CLK 34 /* DBx540 only. */ +#define PRCMU_HVACLK 35 /* DBx540 only. */ +#define PRCMU_SPARE1CLK 36 +#define PRCMU_SPARE2CLK 37 + +#define PRCMU_NUM_REG_CLOCKS 38 + +#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS +#define PRCMU_SYSCLK 39 +#define PRCMU_CDCLK 40 +#define PRCMU_TIMCLK 41 +#define PRCMU_PLLSOC0 42 +#define PRCMU_PLLSOC1 43 +#define PRCMU_ARMSS 44 +#define PRCMU_PLLDDR 45 + +/* DSI Clocks */ +#define PRCMU_PLLDSI 46 +#define PRCMU_DSI0CLK 47 +#define PRCMU_DSI1CLK 48 +#define PRCMU_DSI0ESCCLK 49 +#define PRCMU_DSI1ESCCLK 50 +#define PRCMU_DSI2ESCCLK 51 + +/* LCD DSI PLL - Ux540 only */ +#define PRCMU_PLLDSI_LCD 52 +#define PRCMU_DSI0CLK_LCD 53 +#define PRCMU_DSI1CLK_LCD 54 +#define PRCMU_DSI0ESCCLK_LCD 55 +#define PRCMU_DSI1ESCCLK_LCD 56 +#define PRCMU_DSI2ESCCLK_LCD 57 + +#define PRCMU_NUM_CLKS 58 + +#endif -- cgit From 689088f9dae8b823651095a34aff76cc61099ef9 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sat, 4 Jan 2020 18:45:17 +0100 Subject: arm: Add support for ST-Ericsson U8500 SoC The NovaThor U8500 SoC was released by ST-Ericsson in 2011. It was used for some development boards like the CALAO Systems Snowball SBC, but mass production was primarily for Android smartphones like the Samsung Galaxy S III mini. Previous support for U8500 was removed in commit 68282f55b846 ("arm: Remove unused ST-Ericsson u8500 arch") since none of the boards were converted to generic boards before the deadline. The new code does not have much in common with the previous code. I have completely rewritten everything, embracing the Driver Model and device trees wherever possible. The U8500 support is a bit more minimal for now - my primary use case is to use U-Boot as alternative bootloader for some of the U8500 Samsung smartphones. At the moment U-Boot is chain-loaded from the original Samsung bootloader. A side effect of this is that we can (temporarily) get away without implementing some functionality - e.g. all clocks are already enabled by the original bootloader. More functionality will be added in future patches. Cc: Mathieu Poirier Cc: John Rigby Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij --- arch/arm/Kconfig | 20 ++++++++++++++++++++ arch/arm/Makefile | 1 + arch/arm/dts/ste-dbx5x0-u-boot.dtsi | 29 +++++++++++++++++++++++++++++ arch/arm/include/asm/gpio.h | 2 +- arch/arm/mach-u8500/Kconfig | 6 ++++++ arch/arm/mach-u8500/Makefile | 4 ++++ arch/arm/mach-u8500/cache.c | 37 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-u8500/cpuinfo.c | 25 +++++++++++++++++++++++++ 8 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ste-dbx5x0-u-boot.dtsi create mode 100644 arch/arm/mach-u8500/Kconfig create mode 100644 arch/arm/mach-u8500/Makefile create mode 100644 arch/arm/mach-u8500/cache.c create mode 100644 arch/arm/mach-u8500/cpuinfo.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a623ef5743..78cc79a235 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1009,6 +1009,24 @@ config ARCH_SUNXI imply SPL_SERIAL_SUPPORT imply USB_GADGET +config ARCH_U8500 + bool "ST-Ericsson U8500 Series" + select CPU_V7A + select DM + select DM_GPIO + select DM_MMC if MMC + select DM_SERIAL + select DM_USB if USB + select OF_CONTROL + select SYSRESET + select TIMER + imply ARM_PL180_MMCI + imply DM_RTC + imply NOMADIK_MTU_TIMER + imply PL01X_SERIAL + imply RTC_PL031 + imply SYSRESET_SYSCON + config ARCH_VERSAL bool "Support Xilinx Versal Platform" select ARM64 @@ -1779,6 +1797,8 @@ source "arch/arm/mach-sunxi/Kconfig" source "arch/arm/mach-tegra/Kconfig" +source "arch/arm/mach-u8500/Kconfig" + source "arch/arm/mach-uniphier/Kconfig" source "arch/arm/cpu/armv7/vf610/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1e60a9fdd4..e25bb0e594 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -79,6 +79,7 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_STM32) += stm32 machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra +machine-$(CONFIG_ARCH_U8500) += u8500 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp diff --git a/arch/arm/dts/ste-dbx5x0-u-boot.dtsi b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi new file mode 100644 index 0000000000..4a99ee5a92 --- /dev/null +++ b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "skeleton.dtsi" +#include "ste-dbx5x0.dtsi" + +/ { + soc { + /* FIXME: Remove this when clk driver is implemented */ + mtu@a03c6000 { + clock-frequency = <133000000>; + }; + uart@80120000 { + clock = <38400000>; + }; + uart@80121000 { + clock = <38400000>; + }; + uart@80007000 { + clock = <38400000>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&prcmu>; + offset = <0x228>; /* PRCM_APE_SOFTRST */ + mask = <0x1>; + }; +}; diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 6ff5f42424..7203ccbaeb 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -3,7 +3,7 @@ !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \ !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \ - !defined(CONFIG_ARCH_ASPEED) + !defined(CONFIG_ARCH_ASPEED) && !defined(CONFIG_ARCH_U8500) #include #endif #include diff --git a/arch/arm/mach-u8500/Kconfig b/arch/arm/mach-u8500/Kconfig new file mode 100644 index 0000000000..3bc76295cb --- /dev/null +++ b/arch/arm/mach-u8500/Kconfig @@ -0,0 +1,6 @@ +if ARCH_U8500 + +config SYS_SOC + default "u8500" + +endif diff --git a/arch/arm/mach-u8500/Makefile b/arch/arm/mach-u8500/Makefile new file mode 100644 index 0000000000..0a53cbd9ac --- /dev/null +++ b/arch/arm/mach-u8500/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += cache.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c new file mode 100644 index 0000000000..3d96d09f31 --- /dev/null +++ b/arch/arm/mach-u8500/cache.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Stephan Gerhold + */ + +#include +#include +#include +#include + +#define PL310_WAY_MASK 0xff + +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#ifdef CONFIG_SYS_L2_PL310 +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + /* + * Linux expects the L2 cache to be turned off by the bootloader. + * Otherwise, it fails very early (shortly after decompressing the kernel). + * + * On U8500, the L2 cache can be only turned on/off from the secure world. + * Instead, prevent usage of the L2 cache by locking all ways. + * The kernel needs to unlock them to make the L2 cache work again. + */ + writel(PL310_WAY_MASK, &pl310->pl310_lockdown_dbase); + writel(PL310_WAY_MASK, &pl310->pl310_lockdown_ibase); +} +#endif diff --git a/arch/arm/mach-u8500/cpuinfo.c b/arch/arm/mach-u8500/cpuinfo.c new file mode 100644 index 0000000000..20f5ff3398 --- /dev/null +++ b/arch/arm/mach-u8500/cpuinfo.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Stephan Gerhold + */ + +#include +#include + +#define U8500_BOOTROM_BASE 0x90000000 +#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) + +int print_cpuinfo(void) +{ + /* Convert ASIC ID to display string, e.g. 0x8520A0 => DB8520 V1.0 */ + u32 asicid = readl(U8500_ASIC_ID_LOC_V2); + u32 cpu = (asicid >> 8) & 0xffff; + u32 rev = asicid & 0xff; + + /* 0xA0 => 0x10 (V1.0) */ + if (rev >= 0xa0) + rev -= 0x90; + + printf("CPU: ST-Ericsson DB%x V%d.%d\n", cpu, rev >> 4, rev & 0xf); + return 0; +} -- cgit From 293f9ebb9457c1d1e4b6920a21cc9055f2e49b6b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sat, 4 Jan 2020 18:45:18 +0100 Subject: MAINTAINERS: Add ARM U8500 Add myself as maintainer for ST-Ericsson U8500 SoC to MAINTAINERS. Linus Walleij usually reviews all Ux500 related patches, so add him as a reviewer. Cc: Linus Walleij Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9ececd4b80..f03e4262d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -403,6 +403,14 @@ F: arch/arm/mach-keystone/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ +ARM U8500 +M: Stephan Gerhold +R: Linus Walleij +S: Maintained +F: arch/arm/dts/ste-* +F: arch/arm/mach-u8500/ +F: drivers/timer/nomadik-mtu-timer.c + ARM UNIPHIER M: Masahiro Yamada S: Maintained -- cgit From 43d28855d8ed7929856e376524eb41a74731aed1 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sat, 4 Jan 2020 18:45:19 +0100 Subject: board: Add new Samsung "stemmy" board based on ST-Ericsson U8500 The ST-Ericsson U8500 SoC has been used in mass-production for some Android smartphones released around 2012. In particular, Samsung has released more than 5 different smartphones based on U8500, e.g. - Samsung Galaxy S III mini (GT-I8190) "golden" - Samsung Galaxy S Advance (GT-I9070) "janice" - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" and a few others. Mainline Linux has great support for the Ux500 SoC, so these smartphones can also run Linux mainline quite well. Unfortunately, the original Samsung bootloader used on these devices has limitations that prevent booting Linux mainline directly. It keeps the L2 cache enabled, which causes Linux to crash very early, shortly after decompressing the kernel. Using U-Boot allows to circumvent these limitations. We can let the Samsung bootloader chain-load U-Boot and U-Boot locks the L2 cache before booting into Linux. U-Boot has several other advantages - it supports device-trees directly and we are no longer limited to flashing Android boot images through Samsung's proprietary download mode. The Samsung "stemmy" board covers all Samsung devices based on U8500. Add minimal support for "stemmy". For now only UART is supported but this will be extended later. Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij --- arch/arm/dts/Makefile | 2 ++ arch/arm/dts/ste-ux500-samsung-stemmy.dts | 20 +++++++++++++ arch/arm/mach-u8500/Kconfig | 21 +++++++++++++ board/ste/stemmy/Kconfig | 12 ++++++++ board/ste/stemmy/MAINTAINERS | 6 ++++ board/ste/stemmy/Makefile | 2 ++ board/ste/stemmy/README | 49 +++++++++++++++++++++++++++++++ board/ste/stemmy/stemmy.c | 18 ++++++++++++ configs/stemmy_defconfig | 18 ++++++++++++ include/configs/stemmy.h | 29 ++++++++++++++++++ 10 files changed, 177 insertions(+) create mode 100644 arch/arm/dts/ste-ux500-samsung-stemmy.dts create mode 100644 board/ste/stemmy/Kconfig create mode 100644 board/ste/stemmy/MAINTAINERS create mode 100644 board/ste/stemmy/Makefile create mode 100644 board/ste/stemmy/README create mode 100644 board/ste/stemmy/stemmy.c create mode 100644 configs/stemmy_defconfig create mode 100644 include/configs/stemmy.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44f742017e..38d0c2a92c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -389,6 +389,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb +dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb + dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ stm32429i-eval.dtb \ stm32f469-disco.dtb diff --git a/arch/arm/dts/ste-ux500-samsung-stemmy.dts b/arch/arm/dts/ste-ux500-samsung-stemmy.dts new file mode 100644 index 0000000000..7e7f4c823a --- /dev/null +++ b/arch/arm/dts/ste-ux500-samsung-stemmy.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "ste-dbx5x0-u-boot.dtsi" +#include "ste-ab8500.dtsi" + +/ { + compatible = "samsung,stemmy", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + soc { + /* Debugging console UART */ + uart@80007000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/mach-u8500/Kconfig b/arch/arm/mach-u8500/Kconfig index 3bc76295cb..7478deb25f 100644 --- a/arch/arm/mach-u8500/Kconfig +++ b/arch/arm/mach-u8500/Kconfig @@ -3,4 +3,25 @@ if ARCH_U8500 config SYS_SOC default "u8500" +choice + prompt "U8500 board selection" + +config TARGET_STEMMY + bool "Samsung (stemmy) board" + help + The Samsung "stemmy" board supports Samsung smartphones released with + the ST-Ericsson NovaThor U8500 SoC, e.g. + + - Samsung Galaxy S III mini (GT-I8190) "golden" + - Samsung Galaxy S Advance (GT-I9070) "janice" + - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" + + and likely others as well (untested). + + See board/ste/stemmy/README for details. + +endchoice + +source "board/ste/stemmy/Kconfig" + endif diff --git a/board/ste/stemmy/Kconfig b/board/ste/stemmy/Kconfig new file mode 100644 index 0000000000..b890ba51cb --- /dev/null +++ b/board/ste/stemmy/Kconfig @@ -0,0 +1,12 @@ +if TARGET_STEMMY + +config SYS_BOARD + default "stemmy" + +config SYS_VENDOR + default "ste" + +config SYS_CONFIG_NAME + default "stemmy" + +endif diff --git a/board/ste/stemmy/MAINTAINERS b/board/ste/stemmy/MAINTAINERS new file mode 100644 index 0000000000..37daabea9c --- /dev/null +++ b/board/ste/stemmy/MAINTAINERS @@ -0,0 +1,6 @@ +STEMMY BOARD +M: Stephan Gerhold +S: Maintained +F: board/ste/stemmy/ +F: include/configs/stemmy.h +F: configs/stemmy_defconfig diff --git a/board/ste/stemmy/Makefile b/board/ste/stemmy/Makefile new file mode 100644 index 0000000000..1245099bc9 --- /dev/null +++ b/board/ste/stemmy/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y := stemmy.o diff --git a/board/ste/stemmy/README b/board/ste/stemmy/README new file mode 100644 index 0000000000..81f72426f2 --- /dev/null +++ b/board/ste/stemmy/README @@ -0,0 +1,49 @@ +ST-Ericsson U8500 Samsung "stemmy" board +======================================== + +The "stemmy" board supports Samsung smartphones released with +the ST-Ericsson NovaThor U8500 SoC, e.g. + + - Samsung Galaxy S III mini (GT-I8190) "golden" + - Samsung Galaxy S Advance (GT-I9070) "janice" + - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" + +and likely others as well (untested). + +At the moment, U-Boot is intended to be chain-loaded from +the original Samsung bootloader, not replacing it entirely. + +Installation +------------ + +1. Setup cross compiler, e.g. export CROSS_COMPILE=arm-none-eabi- +2. make stemmy_defconfig +3. make + +For newer devices (golden and skomer), the U-Boot binary has to be packed into +an Android boot image. janice boots the raw U-Boot binary from the boot partition. + +4. Obtain mkbootimg, e.g. https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg +5. mkbootimg \ + --kernel=u-boot.bin \ + --base=0x00000000 \ + --kernel_offset=0x00100000 \ + --ramdisk_offset=0x02000000 \ + --tags_offset=0x00000100 \ + --output=u-boot.img + +6. Enter Samsung download mode (press Power + Home + Volume Down) +7. Flash U-Boot image to Android boot partition using Heimdall: + https://gitlab.com/BenjaminDobell/Heimdall + + heimdall flash --Kernel u-boot.(bin|img) + +8. After reboot U-Boot prompt should appear via UART. + +UART +---- + +UART is available through the micro USB port, similar to the Carkit standard. +With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-. + +Make sure to connect the UART cable *before* turning on the phone. diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c new file mode 100644 index 0000000000..8cf6f18755 --- /dev/null +++ b/board/ste/stemmy/stemmy.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Stephan Gerhold + */ +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_init(void) +{ + return 0; +} diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig new file mode 100644 index 0000000000..6908ef3448 --- /dev/null +++ b/configs/stemmy_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_U8500=y +CONFIG_SYS_TEXT_BASE=0x100000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CONFIG=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_GETTIME=y +CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy" +# CONFIG_NET is not set +# CONFIG_MMC_HW_PARTITIONING is not set +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h new file mode 100644 index 0000000000..922eec43ee --- /dev/null +++ b/include/configs/stemmy.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Stephan Gerhold + */ +#ifndef __CONFIGS_STEMMY_H +#define __CONFIGS_STEMMY_H + +#include + +#define CONFIG_SKIP_LOWLEVEL_INIT /* Loaded by another bootloader */ +#define CONFIG_SYS_MALLOC_LEN SZ_2M + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CONFIG_SYS_INIT_RAM_SIZE 0x00100000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* FIXME: This should be loaded from device tree... */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0xa0412000 + +#define CONFIG_SYS_LOAD_ADDR 0x00100000 + +#endif -- cgit From 602ce1d10695d37f9a72b9cd23500b87050db588 Mon Sep 17 00:00:00 2001 From: "Klaus H. Sorensen" Date: Wed, 11 Dec 2019 11:03:33 +0000 Subject: spl_fit.c: enable loading compressed u-boot from fit image Allow reading compressed content from fit image, even if CONFIG_SPL_OS_BOOT is not set. This allow booting compressed 2nd stage u-boot from fit image. Additionally, do not print warning message if compression node is not found, since it simply implies the content is uncompressed. Signed-off-by: Klaus H. Sorensen Signed-off-by: Rasmus Villemoes --- common/spl/spl_fit.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index ac69d8312e..aef1dbdd49 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -259,11 +259,9 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, debug("%s ", genimg_get_type_name(type)); } - if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) { - if (fit_image_get_comp(fit, node, &image_comp)) - puts("Cannot get image compression format.\n"); - else - debug("%s ", genimg_get_comp_name(image_comp)); + if (IS_ENABLED(CONFIG_SPL_GZIP)) { + fit_image_get_comp(fit, node, &image_comp); + debug("%s ", genimg_get_comp_name(image_comp)); } if (fit_image_get_load(fit, node, &load_addr)) -- cgit From 6124667cd8e644fea2ce2b75b77b83c8207bd3e7 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 31 Dec 2019 18:18:22 +0100 Subject: lib: ignore oid_registry_data.c file The file is generated by scripts/build_OID_registry based on the include/linux/oid_registry.h file. Signed-off-by: Dario Binacchi --- lib/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 lib/.gitignore diff --git a/lib/.gitignore b/lib/.gitignore new file mode 100644 index 0000000000..72ff0e993b --- /dev/null +++ b/lib/.gitignore @@ -0,0 +1 @@ +oid_registry_data.c -- cgit From e605ab8483800465df9a72c56cf00034ebe6993d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 1 Jan 2020 15:52:31 +0100 Subject: trace: provide Sphinx style comments Correct some function comments. Convert to Sphinx style. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- lib/trace.c | 54 ++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/lib/trace.c b/lib/trace.c index 6716c7c2f0..ea8c8e0d40 100644 --- a/lib/trace.c +++ b/lib/trace.c @@ -130,13 +130,13 @@ static void __attribute__((no_instrument_function)) add_textbase(void) } /** - * This is called on every function entry + * __cyg_profile_func_enter() - record function entry * * We add to our tally for this function and add to the list of called * functions. * - * @param func_ptr Pointer to function being entered - * @param caller Pointer to function which called this function + * @func_ptr: pointer to function being entered + * @caller: pointer to function which called this function */ void __attribute__((no_instrument_function)) __cyg_profile_func_enter( void *func_ptr, void *caller) @@ -161,12 +161,10 @@ void __attribute__((no_instrument_function)) __cyg_profile_func_enter( } /** - * This is called on every function exit + * __cyg_profile_func_exit() - record function exit * - * We do nothing here. - * - * @param func_ptr Pointer to function being entered - * @param caller Pointer to function which called this function + * @func_ptr: pointer to function being entered + * @caller: pointer to function which called this function */ void __attribute__((no_instrument_function)) __cyg_profile_func_exit( void *func_ptr, void *caller) @@ -180,16 +178,16 @@ void __attribute__((no_instrument_function)) __cyg_profile_func_exit( } /** - * Produce a list of called functions + * trace_list_functions() - produce a list of called functions * * The information is written into the supplied buffer - a header followed * by a list of function records. * - * @param buff Buffer to place list into - * @param buff_size Size of buffer - * @param needed Returns size of buffer needed, which may be - * greater than buff_size if we ran out of space. - * @return 0 if ok, -1 if space was exhausted + * @buff: buffer to place list into + * @buff_size: size of buffer + * @needed: returns size of buffer needed, which may be + * greater than buff_size if we ran out of space. + * Return: 0 if ok, -ENOSPC if space was exhausted */ int trace_list_functions(void *buff, size_t buff_size, size_t *needed) { @@ -236,6 +234,18 @@ int trace_list_functions(void *buff, size_t buff_size, size_t *needed) return 0; } +/** + * trace_list_functions() - produce a list of function calls + * + * The information is written into the supplied buffer - a header followed + * by a list of function records. + * + * @buff: buffer to place list into + * @buff_size: size of buffer + * @needed: returns size of buffer needed, which may be + * greater than buff_size if we ran out of space. + * Return: 0 if ok, -ENOSPC if space was exhausted + */ int trace_list_calls(void *buff, size_t buff_size, size_t *needed) { struct trace_output_hdr *output_hdr = NULL; @@ -281,7 +291,9 @@ int trace_list_calls(void *buff, size_t buff_size, size_t *needed) return 0; } -/* Print basic information about tracing */ +/** + * trace_print_stats() - print basic information about tracing + */ void trace_print_stats(void) { ulong count; @@ -320,10 +332,11 @@ void __attribute__((no_instrument_function)) trace_set_enabled(int enabled) } /** - * Init the tracing system ready for used, and enable it + * trace_init() - initialize the tracing system and enable it * - * @param buff Pointer to trace buffer - * @param buff_size Size of trace buffer + * @buff: Pointer to trace buffer + * @buff_size: Size of trace buffer + * Return: 0 if ok */ int __attribute__((no_instrument_function)) trace_init(void *buff, size_t buff_size) @@ -385,6 +398,11 @@ int __attribute__((no_instrument_function)) trace_init(void *buff, } #ifdef CONFIG_TRACE_EARLY +/** + * trace_early_init() - initialize the tracing system for early tracing + * + * Return: 0 if ok, -ENOSPC if not enough memory is available + */ int __attribute__((no_instrument_function)) trace_early_init(void) { ulong func_count = gd->mon_len / FUNC_SITE_SIZE; -- cgit From e9c669867a8473116673a1e996ff74bbb1867f55 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 3 Dec 2019 09:38:35 +0100 Subject: cmd: pxe: execute the cls command only when supported Execute the command cls (for clear screen), when the "menu background" keyword is present in extlinux.conf file, only if the command is supported. This patch avoid the warning "Unknown command 'cls'" with "menu background" in extlinux.conf when CONFIG_CMD_BMP is activated and CONFIG_CMD_CLS not activated (default for CONFIG_DM_VIDEO). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- cmd/pxe_utils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cmd/pxe_utils.c b/cmd/pxe_utils.c index 8b830212ce..53af04d7dc 100644 --- a/cmd/pxe_utils.c +++ b/cmd/pxe_utils.c @@ -1312,7 +1312,8 @@ void handle_pxe_menu(cmd_tbl_t *cmdtp, struct pxe_menu *cfg) /* display BMP if available */ if (cfg->bmp) { if (get_relfile(cmdtp, cfg->bmp, image_load_addr)) { - run_command("cls", 0); + if (CONFIG_IS_ENABLED(CMD_CLS)) + run_command("cls", 0); bmp_display(image_load_addr, BMP_ALIGN_CENTER, BMP_ALIGN_CENTER); } else { -- cgit From 05bd943aa94154afc2f60cfc14e1a7f51b03710b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 7 Jan 2020 15:50:32 -0300 Subject: Makefile: Let mrproper remove flash.bin and flash.log In order to generate a bootable U-Boot binary for i.MX8QXP MEK we need to run: $ make imx8qxp_mek_defconfig $ make flash.bin The resultant flash.bin and flash.log are not removed after running 'make mrproper'. Include these files into the CLEAN_FILES list entry so that they can be properly deleted after 'make mrproper'. Signed-off-by: Fabio Estevam --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9d7d8c269c..880ffacbc2 100644 --- a/Makefile +++ b/Makefile @@ -1932,7 +1932,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \ boot* u-boot* MLO* SPL System.map fit-dtb.blob* \ u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \ - idbloader.img + idbloader.img flash.bin flash.log # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl \ -- cgit From 6454e95f4f2de75b9eb9d9d1c327cfe6399821dc Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:10 +0100 Subject: bcm68360: add initial support This add the initial support of the broadcom bcm68360 SoC family. Signed-off-by: Philippe Reynes --- arch/arm/Kconfig | 6 ++ arch/arm/dts/bcm68360.dtsi | 217 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 arch/arm/dts/bcm68360.dtsi diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 78cc79a235..94a649f933 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -633,6 +633,12 @@ config ARCH_BCM63158 select OF_CONTROL imply CMD_DM +config ARCH_BCM68360 + bool "Broadcom BCM68360 family" + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_BCM6858 bool "Broadcom BCM6858 family" select DM diff --git a/arch/arm/dts/bcm68360.dtsi b/arch/arm/dts/bcm68360.dtsi new file mode 100644 index 0000000000..7bbe207794 --- /dev/null +++ b/arch/arm/dts/bcm68360.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,bcm68360"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + spi0 = &hsspi; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-pre-reloc; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_osc>; + clock-mult = <2>; + clock-div = <1>; + }; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + + wdt1: watchdog@ff800480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff800480 0x0 0x14>; + clocks = <&refclk50mhz>; + }; + + wdt2: watchdog@ff8004c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff8004c0 0x0 0x14>; + clocks = <&refclk50mhz>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + + uart0: serial@ff800640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x0 0xff800640 0x0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + leds: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x0 0xff800800 0x0 0xe4>; + + status = "disabled"; + }; + + gpio0: gpio-controller@0xff800500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800500 0x0 0x4>, + <0x0 0xff800520 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@0xff800504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800504 0x0 0x4>, + <0x0 0xff800524 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio2: gpio-controller@0xff800508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800508 0x0 0x4>, + <0x0 0xff800528 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio3: gpio-controller@0xff80050c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff80050c 0x0 0x4>, + <0x0 0xff80052c 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio4: gpio-controller@0xff800510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800510 0x0 0x4>, + <0x0 0xff800530 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio5: gpio-controller@0xff800514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800514 0x0 0x4>, + <0x0 0xff800534 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio6: gpio-controller@0xff800518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff800518 0x0 0x4>, + <0x0 0xff800538 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio7: gpio-controller@0xff80051c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x0 0xff80051c 0x0 0x4>, + <0x0 0xff80053c 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + hsspi: spi-controller@ff801000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff801000 0x0 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + + nand: nand-controller@ff801800 { + compatible = "brcm,nand-bcm68360", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x0 0xff801800 0x0 0x180>, + <0x0 0xff802000 0x0 0x10>, + <0x0 0xff801c00 0x0 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; + }; +}; -- cgit From d0edec667fe0a67002992f2f349147a2e9a6fb66 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:11 +0100 Subject: watchdog: bcm6345: allow to use this driver on arm bcm68360 This IP is also used on some arm SoC, so we allow to use it on arm bcm68360 too. Signed-off-by: Philippe Reynes --- drivers/watchdog/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8c16d69d33..2b8064dfae 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -85,7 +85,8 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" - depends on WDT && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) + depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \ + ARCH_BCM6858 || ARCH_BCM63158) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. -- cgit From 34fdacb07b9dbbaa00faa13bf90bd362eae1b6fb Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:12 +0100 Subject: spi: bcm63xx-hsspi: allow to use this driver on arm bcm68360 This IP is also used on some arm SoC, so we allow to use it on arm bcm68360 too. Signed-off-by: Philippe Reynes --- drivers/spi/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fae2040af8..73d1a69807 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -84,7 +84,8 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) + depends on (ARCH_BMIPS || ARCH_BCM68360 || \ + ARCH_BCM6858 || ARCH_BCM63158) help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom -- cgit From 145330112235f1a9e8c289d09878c4e6b900b3c3 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:13 +0100 Subject: nand: brcmnand: add bcm68360 support This adds the nand support for chipset bcm68360. Signed-off-by: Philippe Reynes --- drivers/mtd/nand/raw/Kconfig | 6 ++ drivers/mtd/nand/raw/brcmnand/Makefile | 1 + drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c | 123 ++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5de72fb46c..7814d84ba0 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -78,6 +78,12 @@ config NAND_BRCMNAND_6368 help Enable support for broadcom nand driver on bcm6368. +config NAND_BRCMNAND_68360 + bool "Support Broadcom NAND controller on bcm68360" + depends on NAND_BRCMNAND && ARCH_BCM68360 + help + Enable support for broadcom nand driver on bcm68360. + config NAND_BRCMNAND_6838 bool "Support Broadcom NAND controller on bcm6838" depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 7e70b859dc..5d9e7e3f3b 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o +obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c new file mode 100644 index 0000000000..0f1a28e476 --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "brcmnand.h" + +struct bcm68360_nand_soc { + struct brcmnand_soc soc; + void __iomem *base; +}; + +#define BCM68360_NAND_INT 0x00 +#define BCM68360_NAND_STATUS_SHIFT 0 +#define BCM68360_NAND_STATUS_MASK (0xfff << BCM68360_NAND_STATUS_SHIFT) + +#define BCM68360_NAND_INT_EN 0x04 +#define BCM68360_NAND_ENABLE_SHIFT 0 +#define BCM68360_NAND_ENABLE_MASK (0xffff << BCM68360_NAND_ENABLE_SHIFT) + +enum { + BCM68360_NP_READ = BIT(0), + BCM68360_BLOCK_ERASE = BIT(1), + BCM68360_COPY_BACK = BIT(2), + BCM68360_PAGE_PGM = BIT(3), + BCM68360_CTRL_READY = BIT(4), + BCM68360_DEV_RBPIN = BIT(5), + BCM68360_ECC_ERR_UNC = BIT(6), + BCM68360_ECC_ERR_CORR = BIT(7), +}; + +static bool bcm68360_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct bcm68360_nand_soc *priv = + container_of(soc, struct bcm68360_nand_soc, soc); + void __iomem *mmio = priv->base + BCM68360_NAND_INT; + u32 val = brcmnand_readl(mmio); + + if (val & (BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT)) { + /* Ack interrupt */ + val &= ~BCM68360_NAND_STATUS_MASK; + val |= BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT; + brcmnand_writel(val, mmio); + return true; + } + + return false; +} + +static void bcm68360_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct bcm68360_nand_soc *priv = + container_of(soc, struct bcm68360_nand_soc, soc); + void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN; + u32 val = brcmnand_readl(mmio); + + /* Don't ack any interrupts */ + val &= ~BCM68360_NAND_STATUS_MASK; + + if (en) + val |= BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT; + else + val &= ~(BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT); + + brcmnand_writel(val, mmio); +} + +static int bcm68360_nand_probe(struct udevice *dev) +{ + struct udevice *pdev = dev; + struct bcm68360_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc; + struct resource res; + + soc = &priv->soc; + + dev_read_resource_byname(pdev, "nand-int-base", &res); + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + soc->ctlrdy_ack = bcm68360_nand_intc_ack; + soc->ctlrdy_set_enabled = bcm68360_nand_intc_set; + + /* Disable and ack all interrupts */ + brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN); + brcmnand_writel(0, priv->base + BCM68360_NAND_INT); + + return brcmnand_probe(pdev, soc); +} + +static const struct udevice_id bcm68360_nand_dt_ids[] = { + { + .compatible = "brcm,nand-bcm68360", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm68360_nand) = { + .name = "bcm68360-nand", + .id = UCLASS_MTD, + .of_match = bcm68360_nand_dt_ids, + .probe = bcm68360_nand_probe, + .priv_auto_alloc_size = sizeof(struct bcm68360_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(bcm68360_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} -- cgit From 5602e21ca7b049242445543f564b14b95fe35b72 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:14 +0100 Subject: led: bcm6858: allow to use this driver on arm bcm68360 This IP is also used on some arm SoC, so we allow to use it on arm bcm68360 too. Signed-off-by: Philippe Reynes --- drivers/led/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 5643939348..667593405e 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -30,7 +30,7 @@ config LED_BCM6358 config LED_BCM6858 bool "LED Support for BCM6858" - depends on LED && (ARCH_BCM6858 || ARCH_BCM63158) + depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || ARCH_BCM63158) help This option enables support for LEDs connected to the BCM6858 HW has blinking capabilities and up to 32 LEDs can be controlled. -- cgit From 17f34ca803a264324f79a798b6969d4b0cda1753 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:15 +0100 Subject: gpio: bcm6345: allow to use this driver on arm bcm68360 This IP is also used on some arm SoC, so we allow to use it on arm bcm68360 too. Signed-off-by: Philippe Reynes --- drivers/gpio/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1de6f5225e..4e5a70780a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -55,7 +55,8 @@ config ALTERA_PIO config BCM6345_GPIO bool "BCM6345 GPIO driver" - depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) + depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ + ARCH_BCM6858 || ARCH_BCM63158) help This driver supports the GPIO banks on BCM6345 SoCs. -- cgit From e520036f9d83899eba3707bf2a5eb4c1bf92df55 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:16 +0100 Subject: gpio: do not include on ARCH_BCM68360 As no gpio.h is defined for this architecture, to avoid compilation failure, do not include for arch bcm68360. Signed-off-by: Philippe Reynes --- arch/arm/include/asm/gpio.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 7203ccbaeb..acb7ea9a3e 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,9 +1,10 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ - !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \ - !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ - !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \ - !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \ - !defined(CONFIG_ARCH_ASPEED) && !defined(CONFIG_ARCH_U8500) + !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ + !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ + !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ + !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ + !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_U8500) #include #endif #include -- cgit From 645b7ec52c575e853ef93eddc0f7f16c99f74e55 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Tue, 7 Jan 2020 20:14:17 +0100 Subject: bcm968360bg: add initial support This add the initial support of the broadcom reference board bcm968360bg with a bcm68360 SoC. This board has 512 MB of RAM, 256 MB of flash (nand), 2 USB port, 1 UART, and 4 ethernet ports. Signed-off-by: Philippe Reynes --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/bcm968360bg.dts | 168 +++++++++++++++++++++++++++++++ board/broadcom/bcm968360bg/Kconfig | 17 ++++ board/broadcom/bcm968360bg/MAINTAINERS | 6 ++ board/broadcom/bcm968360bg/Makefile | 3 + board/broadcom/bcm968360bg/bcm968360bg.c | 61 +++++++++++ configs/bcm968360bg_ram_defconfig | 53 ++++++++++ include/configs/broadcom_bcm968360bg.h | 40 ++++++++ 9 files changed, 352 insertions(+) create mode 100644 arch/arm/dts/bcm968360bg.dts create mode 100644 board/broadcom/bcm968360bg/Kconfig create mode 100644 board/broadcom/bcm968360bg/MAINTAINERS create mode 100644 board/broadcom/bcm968360bg/Makefile create mode 100644 board/broadcom/bcm968360bg/bcm968360bg.c create mode 100644 configs/bcm968360bg_ram_defconfig create mode 100644 include/configs/broadcom_bcm968360bg.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 94a649f933..9608f54804 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1834,6 +1834,7 @@ source "board/armltd/vexpress64/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" +source "board/broadcom/bcm968360bg/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 38d0c2a92c..b48b05fd24 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -859,6 +859,9 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ dtb-$(CONFIG_ARCH_BCM63158) += \ bcm963158.dtb +dtb-$(CONFIG_ARCH_BCM68360) += \ + bcm968360bg.dtb + dtb-$(CONFIG_ARCH_BCM6858) += \ bcm968580xref.dtb diff --git a/arch/arm/dts/bcm968360bg.dts b/arch/arm/dts/bcm968360bg.dts new file mode 100644 index 0000000000..c060294cc9 --- /dev/null +++ b/arch/arm/dts/bcm968360bg.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +/dts-v1/; + +#include "bcm68360.dtsi" + +/ { + model = "Broadcom bcm68360bg"; + compatible = "broadcom,bcm68360bg", "brcm,bcm68360"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&gpio7 { + status = "okay"; +}; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; + +&leds { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + brcm,serial-led-en-pol; + brcm,serial-led-data-ppol; + + led@0 { + reg = <0>; + label = "red:alarm"; + }; + + led@1 { + reg = <1>; + label = "green:wan"; + }; + + led@2 { + reg = <2>; + label = "green:wps"; + }; + + led@12 { + reg = <12>; + label = "orange:enet5.1"; + }; + + led@13 { + reg = <13>; + label = "green:enet5.2"; + }; + + led@14 { + reg = <14>; + label = "orange:enet5.2"; + }; + + led@15 { + reg = <15>; + label = "green:enet5.1"; + }; + + led@16 { + reg = <16>; + label = "green:usb1"; + }; + + led@17 { + reg = <17>; + label = "green:voip1"; + }; + + led@18 { + reg = <18>; + label = "green:voip2"; + }; + + led@19 { + reg = <19>; + label = "green:enet6"; + }; + + led@20 { + reg = <20>; + label = "orange:enet6"; + }; + + led@21 { + reg = <21>; + label = "green:inet"; + }; + + led@22 { + reg = <22>; + label = "green:usb2"; + }; +}; + +&hsspi { + status = "okay"; + + flash: mt25@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; diff --git a/board/broadcom/bcm968360bg/Kconfig b/board/broadcom/bcm968360bg/Kconfig new file mode 100644 index 0000000000..dd372f126a --- /dev/null +++ b/board/broadcom/bcm968360bg/Kconfig @@ -0,0 +1,17 @@ +if ARCH_BCM68360 + +config SYS_VENDOR + default "broadcom" + +config SYS_BOARD + default "bcm968360bg" + +config SYS_CONFIG_NAME + default "broadcom_bcm968360bg" + +endif + +config TARGET_BCM968360BG + bool "Support Broadcom bcm968360bg" + depends on ARCH_BCM68360 + select ARM64 diff --git a/board/broadcom/bcm968360bg/MAINTAINERS b/board/broadcom/bcm968360bg/MAINTAINERS new file mode 100644 index 0000000000..cfcbbc51f8 --- /dev/null +++ b/board/broadcom/bcm968360bg/MAINTAINERS @@ -0,0 +1,6 @@ +BCM968360BG BOARD +M: Philippe Reynes +S: Maintained +F: board/broadcom/bcm968360bg +F: include/configs/broadcom_bcm968360bg.h +F: configs/bcm968360bg_ram_defconfig diff --git a/board/broadcom/bcm968360bg/Makefile b/board/broadcom/bcm968360bg/Makefile new file mode 100644 index 0000000000..d099c1cf35 --- /dev/null +++ b/board/broadcom/bcm968360bg/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bcm968360bg.o diff --git a/board/broadcom/bcm968360bg/bcm968360bg.c b/board/broadcom/bcm968360bg/bcm968360bg.c new file mode 100644 index 0000000000..a5fbc1d297 --- /dev/null +++ b/board/broadcom/bcm968360bg/bcm968360bg.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include +#include +#include + +#ifdef CONFIG_ARM64 +#include + +static struct mm_region broadcom_bcm968360bg_mem_map[] = { + { + /* RAM */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* SoC */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0xff80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = broadcom_bcm968360bg_mem_map; +#endif + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + printf("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} diff --git a/configs/bcm968360bg_ram_defconfig b/configs/bcm968360bg_ram_defconfig new file mode 100644 index 0000000000..4a4c1fd1c7 --- /dev/null +++ b/configs/bcm968360bg_ram_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCM68360=y +CONFIG_SYS_TEXT_BASE=0x10000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TARGET_BCM968360BG=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_BCM6345_GPIO=y +CONFIG_LED=y +CONFIG_LED_BCM6858=y +CONFIG_LED_BLINK=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_68360=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_SEARCH_ALL=y +CONFIG_BCM6345_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCM63XX_HSSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h new file mode 100644 index 0000000000..77690ff40f --- /dev/null +++ b/include/configs/broadcom_bcm968360bg.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* + * 6858 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ + +/* + * 968360bg + */ -- cgit From 9086ab564b93a51d3cb18deb7ac59179e2541285 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 8 Jan 2020 20:21:17 +0900 Subject: board_init: remove meaningless increment in board_init_f_init_reserve() The base is not used in the code that follows this increment. Signed-off-by: Masahiro Yamada --- common/init/board_init.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/common/init/board_init.c b/common/init/board_init.c index 3bc7994586..f7c8a173ff 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -157,8 +157,6 @@ void board_init_f_init_reserve(ulong base) #if CONFIG_VAL(SYS_MALLOC_F_LEN) /* go down one 'early malloc arena' */ gd->malloc_base = base; - /* next alloc will be higher by one 'early malloc arena' size */ - base += CONFIG_VAL(SYS_MALLOC_F_LEN); #endif if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)) -- cgit From 04cd7108e6271d0a83e70444ddd4e12902253a44 Mon Sep 17 00:00:00 2001 From: Matthias Schoepfer Date: Thu, 9 Jan 2020 16:53:32 +0100 Subject: removing fdt_high from default set of variables for, dragonboard410c config When using fitImage in AARCH64, the fdt is only 4 byte aligned. According to linux kernel -> Documentation/arm64/booting.txt, the fdt *must* be 8 byte aligned. Therefore, it is somewhat random, if you build a kernel that the fdt is 4 or 8 byte aligned. Removing fdt_high (or changing it to a valid 8 byte aligned address) solves this issue. Signed-off-by: Matthias Schoepfer CC: Mateusz Kulikowski --- include/configs/dragonboard410c.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 65149ad441..9362e9322c 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -69,7 +69,6 @@ REFLASH(dragonboard/u-boot.img, 8)\ #define CONFIG_EXTRA_ENV_SETTINGS \ "reflash="CONFIG_ENV_REFLASH"\0"\ "loadaddr=0x81000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "linux_image=Image\0" \ "kernel_addr_r=0x81000000\0"\ -- cgit From 3e6359830854bf1ed43f255d5248fbd267de26c4 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 10 Jan 2020 15:53:51 +0530 Subject: MAINTAINERS: Add entry for rng drivers Take up maintainership of random number generator drivers with Heinrich Schuchardt as the reviewer. Signed-off-by: Sughosh Ganu Reviewed-by: Heinrich Schuchardt --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f03e4262d2..b0634b23bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -789,6 +789,15 @@ F: arch/riscv/ F: cmd/riscv/ F: tools/prelink-riscv.c +RNG +M: Sughosh Ganu +R: Heinrich Schuchardt +S: Maintained +F: cmd/rng.c +F: drivers/rng/ +F: drivers/virtio/virtio_rng.c +F: include/rng.h + ROCKUSB M: Eddie Cai S: Maintained -- cgit From ac32e7d109112f848b3f0dc68cff48021e348e86 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 10 Jan 2020 12:47:41 +0100 Subject: kmp204x: do not make FPGA config error fail board_early_init_r This prevents the board from booting which is not the expected behavior. Signed-off-by: Valentin Longchamp Signed-off-by: Holger Brunck CC: Priyanka Jain --- board/keymile/kmp204x/kmp204x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index cfb23a53f7..c93fa3c62e 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -138,7 +138,7 @@ int board_early_init_r(void) /* enable Application Buffer */ qrio_enable_app_buffer(); - return ret; + return 0; } unsigned long get_board_sys_clk(unsigned long dummy) -- cgit From 78a408bb49a78462b1cdff0611029d8f830c5e5e Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 10 Jan 2020 12:47:42 +0100 Subject: KM/kmp204x: qrio and i2c deblock code moved to common This patch moves the qrio and i2c deblocking code to keymile/common as it will also be used by the upcoming CENT2 board. Signed-off-by: Holger Brunck CC: Priyanka Jain --- board/keymile/common/qrio.c | 280 ++++++++++++++++++++++++++++++++++++++++ board/keymile/common/qrio.h | 40 ++++++ board/keymile/kmp204x/Makefile | 4 +- board/keymile/kmp204x/kmp204x.c | 48 +------ board/keymile/kmp204x/kmp204x.h | 26 ---- board/keymile/kmp204x/pci.c | 15 ++- board/keymile/kmp204x/qrio.c | 206 ----------------------------- include/configs/kmp204x.h | 4 + 8 files changed, 336 insertions(+), 287 deletions(-) create mode 100644 board/keymile/common/qrio.c create mode 100644 board/keymile/common/qrio.h delete mode 100644 board/keymile/kmp204x/qrio.c diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c new file mode 100644 index 0000000000..0641ffa8b2 --- /dev/null +++ b/board/keymile/common/qrio.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + */ + +#include + +#include "common.h" +#include "qrio.h" + +/* QRIO GPIO register offsets */ +#define DIRECT_OFF 0x18 +#define GPRT_OFF 0x1c + +int qrio_get_gpio(u8 port_off, u8 gpio_nr) +{ + u32 gprt; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + + return (gprt >> gpio_nr) & 1U; +} + +void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) +{ + u32 gprt, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + if (value) + gprt |= mask; + else + gprt &= ~mask; + + out_be32(qrio_base + port_off + GPRT_OFF, gprt); +} + +void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct |= mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); + + qrio_set_gpio(port_off, gpio_nr, value); +} + +void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct &= ~mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + if (val == 0) + /* set to output -> GPIO drives low */ + direct |= mask; + else + /* set to input -> GPIO floating */ + direct &= ~mask; + + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +#define WDMASK_OFF 0x16 + +void qrio_wdmask(u8 bit, bool wden) +{ + u16 wdmask; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + wdmask = in_be16(qrio_base + WDMASK_OFF); + + if (wden) + wdmask |= (1 << bit); + else + wdmask &= ~(1 << bit); + + out_be16(qrio_base + WDMASK_OFF, wdmask); +} + +#define PRST_OFF 0x1a + +void qrio_prst(u8 bit, bool en, bool wden) +{ + u16 prst; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + qrio_wdmask(bit, wden); + + prst = in_be16(qrio_base + PRST_OFF); + + if (en) + prst &= ~(1 << bit); + else + prst |= (1 << bit); + + out_be16(qrio_base + PRST_OFF, prst); +} + +#define PRSTCFG_OFF 0x1c + +void qrio_prstcfg(u8 bit, u8 mode) +{ + u32 prstcfg; + u8 i; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + prstcfg = in_be32(qrio_base + PRSTCFG_OFF); + + for (i = 0; i < 2; i++) { + if (mode & (1 << i)) + set_bit(2 * bit + i, &prstcfg); + else + clear_bit(2 * bit + i, &prstcfg); + } + + out_be32(qrio_base + PRSTCFG_OFF, prstcfg); +} + +#define CTRLH_OFF 0x02 +#define CTRLH_WRL_BOOT 0x01 +#define CTRLH_WRL_UNITRUN 0x02 + +void qrio_set_leds(void) +{ + u8 ctrlh; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + /* set UNIT LED to RED and BOOT LED to ON */ + ctrlh = in_8(qrio_base + CTRLH_OFF); + ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN); + out_8(qrio_base + CTRLH_OFF, ctrlh); +} + +#define CTRLL_OFF 0x03 +#define CTRLL_WRB_BUFENA 0x20 + +void qrio_enable_app_buffer(void) +{ + u8 ctrll; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + /* enable application buffer */ + ctrll = in_8(qrio_base + CTRLL_OFF); + ctrll |= (CTRLL_WRB_BUFENA); + out_8(qrio_base + CTRLL_OFF, ctrll); +} + +#define REASON1_OFF 0x12 +#define REASON1_CPUWD 0x01 + +void qrio_cpuwd_flag(bool flag) +{ + u8 reason1; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + reason1 = in_8(qrio_base + REASON1_OFF); + if (flag) + reason1 |= REASON1_CPUWD; + else + reason1 &= ~REASON1_CPUWD; + out_8(qrio_base + REASON1_OFF, reason1); +} + +#define REASON0_OFF 0x13 +#define REASON0_SWURST 0x80 +#define REASON0_CPURST 0x40 +#define REASON0_BPRST 0x20 +#define REASON0_COPRST 0x10 +#define REASON0_SWCRST 0x08 +#define REASON0_WDRST 0x04 +#define REASON0_KBRST 0x02 +#define REASON0_POWUP 0x01 +#define UNIT_RESET\ + ((REASON1_CPUWD << 8) |\ + REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\ + REASON0_BPRST | REASON0_SWURST | REASON0_WDRST) +#define CORE_RESET REASON0_SWCRST + +bool qrio_reason_unitrst(void) +{ + u16 reason; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + reason = in_be16(qrio_base + REASON1_OFF); + + return (reason & UNIT_RESET) > 0; +} + +#define RSTCFG_OFF 0x11 + +void qrio_uprstreq(u8 mode) +{ + u32 rstcfg; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + rstcfg = in_8(qrio_base + RSTCFG_OFF); + + if (mode & UPREQ_CORE_RST) + rstcfg |= UPREQ_CORE_RST; + else + rstcfg &= ~UPREQ_CORE_RST; + + out_8(qrio_base + RSTCFG_OFF, rstcfg); +} + +/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c + * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines + * For I2C only the low state is activly driven and high state is pulled-up + * by a resistor. Therefore the deblock GPIOs are used + * -> as an active output to drive a low state + * -> as an open-drain input to have a pulled-up high state + */ + +/* By default deblock GPIOs are floating */ +void i2c_deblock_gpio_cfg(void) +{ + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ + qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SCL); + qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SDA); + + qrio_set_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SCL, 0); + qrio_set_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SDA, 0); +} + +void set_sda(int state) +{ + qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SDA, state); +} + +void set_scl(int state) +{ + qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SCL, state); +} + +int get_sda(void) +{ + return qrio_get_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SDA); +} + +int get_scl(void) +{ + return qrio_get_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SCL); +} + diff --git a/board/keymile/common/qrio.h b/board/keymile/common/qrio.h new file mode 100644 index 0000000000..a6cfd8165d --- /dev/null +++ b/board/keymile/common/qrio.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 ABB + * Valentin Longchamp + */ + +#ifndef __QRIO_H +#define __QRIO_H + +/* QRIO GPIO ports */ +#define QRIO_GPIO_A 0x40 +#define QRIO_GPIO_B 0x60 + +int qrio_get_gpio(u8 port_off, u8 gpio_nr); +void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); +void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); +void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value); +void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr); + +/* QRIO Periphery reset configurations */ +#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 +#define PRSTCFG_POWUP_UNIT_RST 0x1 +#define PRSTCFG_POWUP_RST 0x3 + +void qrio_prst(u8 bit, bool en, bool wden); +void qrio_wdmask(u8 bit, bool wden); +void qrio_prstcfg(u8 bit, u8 mode); +void qrio_set_leds(void); +void qrio_enable_app_buffer(void); +void qrio_cpuwd_flag(bool flag); +bool qrio_reason_unitrst(void); + +/* QRIO uP reset request configurations */ +#define UPREQ_UNIT_RST 0x0 +#define UPREQ_CORE_RST 0x1 + +void qrio_uprstreq(u8 mode); + +void i2c_deblock_gpio_cfg(void); +#endif /* __QRIO_H */ diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile index 626c627be7..5523ee99aa 100644 --- a/board/keymile/kmp204x/Makefile +++ b/board/keymile/kmp204x/Makefile @@ -6,5 +6,5 @@ # See file CREDITS for list of people who contributed to this # project. -obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \ - ../common/common.o ../common/ivm.o +obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o ../common/common.o\ + ../common/ivm.o ../common/qrio.o diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index c93fa3c62e..0a6cf1fd29 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -24,6 +24,7 @@ #include #include "../common/common.h" +#include "../common/qrio.h" #include "kmp204x.h" static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; @@ -35,51 +36,6 @@ int checkboard(void) return 0; } -/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c - * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines - * For I2C only the low state is activly driven and high state is pulled-up - * by a resistor. Therefore the deblock GPIOs are used - * -> as an active output to drive a low state - * -> as an open-drain input to have a pulled-up high state - */ - -/* QRIO GPIOs used for deblocking */ -#define DEBLOCK_PORT1 GPIO_A -#define DEBLOCK_SCL1 20 -#define DEBLOCK_SDA1 21 - -/* By default deblock GPIOs are floating */ -static void i2c_deblock_gpio_cfg(void) -{ - /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ - qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); - qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); - - qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); - qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); -} - -void set_sda(int state) -{ - qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); -} - -void set_scl(int state) -{ - qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); -} - -int get_sda(void) -{ - return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); -} - -int get_scl(void) -{ - return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); -} - - #define ZL30158_RST 8 #define BFTIC4_RST 0 #define RSTRQSR1_WDT_RR 0x00200000 @@ -297,7 +253,7 @@ int ft_board_setup(void *blob, bd_t *bd) #if defined(CONFIG_POST) /* DIC26_SELFTEST GPIO used to start factory test sw */ -#define SELFTEST_PORT GPIO_A +#define SELFTEST_PORT QRIO_GPIO_A #define SELFTEST_PIN 31 int post_hotkeys_pressed(void) diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h index 4d14c44617..00e1a06662 100644 --- a/board/keymile/kmp204x/kmp204x.h +++ b/board/keymile/kmp204x/kmp204x.h @@ -4,31 +4,5 @@ * Valentin Longchamp */ -/* QRIO GPIO ports */ -#define GPIO_A 0x40 -#define GPIO_B 0x60 - -int qrio_get_gpio(u8 port_off, u8 gpio_nr); -void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); -void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); -void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value); -void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr); - -#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 -#define PRSTCFG_POWUP_UNIT_RST 0x1 -#define PRSTCFG_POWUP_RST 0x3 - -void qrio_prst(u8 bit, bool en, bool wden); -void qrio_wdmask(u8 bit, bool wden); -void qrio_prstcfg(u8 bit, u8 mode); -void qrio_set_leds(void); -void qrio_enable_app_buffer(void); -void qrio_cpuwd_flag(bool flag); -int qrio_reset_reason(void); - -#define UPREQ_UNIT_RST 0x0 -#define UPREQ_CORE_RST 0x1 - -void qrio_uprstreq(u8 mode); void pci_of_setup(void *blob, bd_t *bd); diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c index a8047457f2..15bbc810a1 100644 --- a/board/keymile/kmp204x/pci.c +++ b/board/keymile/kmp204x/pci.c @@ -16,13 +16,14 @@ #include #include +#include "../common/qrio.h" #include "kmp204x.h" #define PROM_SEL_L 11 /* control the PROM_SEL_L signal*/ static void toggle_fpga_eeprom_bus(bool cpu_own) { - qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own); + qrio_gpio_direction_output(QRIO_GPIO_A, PROM_SEL_L, !cpu_own); } #define CONF_SEL_L 10 @@ -40,17 +41,17 @@ int trigger_fpga_config(void) toggle_fpga_eeprom_bus(false); /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ - qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0); + qrio_gpio_direction_output(QRIO_GPIO_A, CONF_SEL_L, 0); /* trigger the config start */ - qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0); + qrio_gpio_direction_output(QRIO_GPIO_A, FPGA_PROG_L, 0); /* small delay for INIT_L line */ udelay(10); /* wait for FPGA_INIT to be asserted */ do { - init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L); + init_l = qrio_get_gpio(QRIO_GPIO_A, FPGA_INIT_L); if (timeout-- == 0) { printf("FPGA_INIT timeout\n"); ret = -EFAULT; @@ -60,7 +61,7 @@ int trigger_fpga_config(void) } while (init_l); /* deassert FPGA_PROG, config should start */ - qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1); + qrio_set_gpio(QRIO_GPIO_A, FPGA_PROG_L, 1); return ret; } @@ -74,7 +75,7 @@ static int wait_for_fpga_config(void) printf("PCIe FPGA config:"); do { - done = qrio_get_gpio(GPIO_A, FPGA_DONE); + done = qrio_get_gpio(QRIO_GPIO_A, FPGA_DONE); if (timeout-- == 0) { printf(" FPGA_DONE timeout\n"); ret = -EFAULT; @@ -87,7 +88,7 @@ static int wait_for_fpga_config(void) err_out: /* deactive CONF_SEL and give the CPU conf EEPROM access */ - qrio_set_gpio(GPIO_A, CONF_SEL_L, 1); + qrio_set_gpio(QRIO_GPIO_A, CONF_SEL_L, 1); toggle_fpga_eeprom_bus(true); return ret; diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c deleted file mode 100644 index 03026a277b..0000000000 --- a/board/keymile/kmp204x/qrio.c +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp - */ - -#include - -#include "../common/common.h" -#include "kmp204x.h" - -/* QRIO GPIO register offsets */ -#define DIRECT_OFF 0x18 -#define GPRT_OFF 0x1c - -int qrio_get_gpio(u8 port_off, u8 gpio_nr) -{ - u32 gprt; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - gprt = in_be32(qrio_base + port_off + GPRT_OFF); - - return (gprt >> gpio_nr) & 1U; -} - -void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) -{ - u32 gprt, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - gprt = in_be32(qrio_base + port_off + GPRT_OFF); - if (value) - gprt |= mask; - else - gprt &= ~mask; - - out_be32(qrio_base + port_off + GPRT_OFF, gprt); -} - -void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) -{ - u32 direct, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - direct = in_be32(qrio_base + port_off + DIRECT_OFF); - direct |= mask; - out_be32(qrio_base + port_off + DIRECT_OFF, direct); - - qrio_set_gpio(port_off, gpio_nr, value); -} - -void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) -{ - u32 direct, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - direct = in_be32(qrio_base + port_off + DIRECT_OFF); - direct &= ~mask; - out_be32(qrio_base + port_off + DIRECT_OFF, direct); -} - -void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) -{ - u32 direct, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - direct = in_be32(qrio_base + port_off + DIRECT_OFF); - if (val == 0) - /* set to output -> GPIO drives low */ - direct |= mask; - else - /* set to input -> GPIO floating */ - direct &= ~mask; - - out_be32(qrio_base + port_off + DIRECT_OFF, direct); -} - -#define WDMASK_OFF 0x16 - -void qrio_wdmask(u8 bit, bool wden) -{ - u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - wdmask = in_be16(qrio_base + WDMASK_OFF); - - if (wden) - wdmask |= (1 << bit); - else - wdmask &= ~(1 << bit); - - out_be16(qrio_base + WDMASK_OFF, wdmask); -} - -#define PRST_OFF 0x1a - -void qrio_prst(u8 bit, bool en, bool wden) -{ - u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - qrio_wdmask(bit, wden); - - prst = in_be16(qrio_base + PRST_OFF); - - if (en) - prst &= ~(1 << bit); - else - prst |= (1 << bit); - - out_be16(qrio_base + PRST_OFF, prst); -} - -#define PRSTCFG_OFF 0x1c - -void qrio_prstcfg(u8 bit, u8 mode) -{ - u32 prstcfg; - u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - prstcfg = in_be32(qrio_base + PRSTCFG_OFF); - - for (i = 0; i < 2; i++) { - if (mode & (1< Date: Fri, 10 Jan 2020 12:47:43 +0100 Subject: km/common: fix for CPUWD reset reason The CPUWD reset reason is used for kmp204x. And the qrio cpu reset request is configured to operate in core reset mode. But for the evaluation of the qrio's reset reason register the CPUWD figures as a unit reset source rather than a core reset source. This patch defines the CPUWD reset as a core reset source when evaluating the reset reason register. Signed-off-by: Rainer Boschung CC: Priyanka Jain --- board/keymile/common/qrio.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 0641ffa8b2..0cb33663aa 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -199,10 +199,9 @@ void qrio_cpuwd_flag(bool flag) #define REASON0_KBRST 0x02 #define REASON0_POWUP 0x01 #define UNIT_RESET\ - ((REASON1_CPUWD << 8) |\ - REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\ - REASON0_BPRST | REASON0_SWURST | REASON0_WDRST) -#define CORE_RESET REASON0_SWCRST + (REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\ + REASON0_BPRST | REASON0_SWURST | REASON0_WDRST) +#define CORE_RESET ((REASON1_CPUWD << 8) | REASON0_SWCRST) bool qrio_reason_unitrst(void) { -- cgit From 27a5f833ff0cc84103e97df207f8bc3c0dd03e6f Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 10 Jan 2020 12:55:41 +0100 Subject: km/scripts: fix run ramfs and COGE5 tftppath problem The tftppath was not set in case of run ramfs. It worked only by chance if was already set before. Also check the boardname before setting the tftppath for COGE5. Signed-off-by: Holger Brunck CC: Tom Rini --- board/keymile/scripts/develop-common.txt | 3 ++- board/keymile/scripts/ramfs-common.txt | 9 +++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index 265f02f4ec..ba15323a5b 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -1,6 +1,6 @@ altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} -configure=run set_uimage; setenv tftppath ${IVM_Symbol} ; km_setboardid && saveenv && reset +configure=run set_uimage; run set_tftppath; km_setboardid && saveenv && reset subbootcmds=tftpfdt tftpkernel nfsargs add_default boot nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch} tftpfdt=if run set_fdthigh || test ${arch} != arm; then if tftpboot ${fdt_addr_r} ${tftppath}/fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; then; else tftpboot ${fdt_addr_r} ${tftppath}/${hostname}.dtb; fi; else true; fi @@ -8,3 +8,4 @@ tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage} toolchain=/opt/eldk rootfssize=0 set_uimage=printenv uimage || setenv uimage uImage +set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index d79ad2e21b..61357e2c34 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -4,10 +4,11 @@ altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} -configure=run set_uimage; km_setboardid && saveenv && reset +configure=run set_uimage; run set_tftppath; km_setboardid && saveenv && reset rootfsfile=${hostname}/rootfsImage setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} -tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi -tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} -tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage +tftpfdt=if run set_fdthigh || test ${arch} != arm; then if tftpboot ${fdt_addr_r} ${tftppath}/fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; then; else tftpboot ${fdt_addr_r} ${tftppath}/${hostname}.dtb; fi; else true; fi +tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage} +tftpramfs=tftpboot ${rootfsaddr} ${tftppath}/rootfsImage set_uimage=printenv uimage || setenv uimage uImage +set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi -- cgit From d4348a8db79de3985c3a6b738056e5b00d4ad020 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 10 Jan 2020 12:55:42 +0100 Subject: km/scripts: product env and auto-reset for ramfs This patch adds the possibility in both debug and ramfs modes to optionally load an env file from /tftpboot/$tftppath (this is ignored if not present, so the change is backward compatible). This gives the debug and ramfs scripts the possibility to set uboot environment variables that were previously asked the users to manually set (nfs path in debug and rootfs size in ramfs). Signed-off-by: Holger Brunck CC: Tom Rini --- board/keymile/scripts/develop-common.txt | 3 ++- board/keymile/scripts/ramfs-common.txt | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index ba15323a5b..f77a26abe8 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -1,6 +1,6 @@ altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} -configure=run set_uimage; run set_tftppath; km_setboardid && saveenv && reset +configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_nfs_path && saveenv && reset subbootcmds=tftpfdt tftpkernel nfsargs add_default boot nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch} tftpfdt=if run set_fdthigh || test ${arch} != arm; then if tftpboot ${fdt_addr_r} ${tftppath}/fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; then; else tftpboot ${fdt_addr_r} ${tftppath}/${hostname}.dtb; fi; else true; fi @@ -9,3 +9,4 @@ toolchain=/opt/eldk rootfssize=0 set_uimage=printenv uimage || setenv uimage uImage set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi +try_import_nfs_path=if tftpboot 0x200000 ${tftppath}/nfs-path.txt; then env import -t 0x200000 ${filesize}; else echo no auto nfs path imported; echo you can set nfsargs in /tftpboot/${tftppath}/nfs-path.txt and rerun develop; fi diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index 61357e2c34..290c602aab 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -2,13 +2,14 @@ addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsadd boot_bank=-1 altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} -subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot +subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot +save_and_reset_once=setenv save_and_reset_once true && save && reset nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} -configure=run set_uimage; run set_tftppath; km_setboardid && saveenv && reset -rootfsfile=${hostname}/rootfsImage +configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_rootfssize && saveenv && reset setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} tftpfdt=if run set_fdthigh || test ${arch} != arm; then if tftpboot ${fdt_addr_r} ${tftppath}/fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; then; else tftpboot ${fdt_addr_r} ${tftppath}/${hostname}.dtb; fi; else true; fi tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage} tftpramfs=tftpboot ${rootfsaddr} ${tftppath}/rootfsImage set_uimage=printenv uimage || setenv uimage uImage set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi +try_import_rootfssize=if tftpboot 0x200000 ${tftppath}/rootfssize.txt; then env import -t 0x200000 ${filesize}; else echo no auto rootfs size; echo you can set rootfssize in /tftpboot/${tftppath}/rootfssize.txt and rerun ramfs; fi -- cgit From 17f084fa8c64c97a68d854bd8611a55f69ac056d Mon Sep 17 00:00:00 2001 From: Joel Johnson Date: Sat, 11 Jan 2020 09:09:34 -0700 Subject: zfs: remove unused buf variable Remove unused variable to silence compiler warning Signed-off-by: Joel Johnson --- cmd/zfs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/cmd/zfs.c b/cmd/zfs.c index 1533130635..9c237a5758 100644 --- a/cmd/zfs.c +++ b/cmd/zfs.c @@ -40,7 +40,6 @@ static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ulong addr = 0; disk_partition_t info; struct blk_desc *dev_desc; - char buf[12]; unsigned long count; const char *addr_str; struct zfs_file zfile; -- cgit From 0e1c0f361edf590fcea9fcab6333d1a142934eeb Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Mon, 13 Jan 2020 15:34:01 +0100 Subject: arm/km: add support for SUSE2 This board is similar to SUV31, but the FPGA is reset concept is quite different. Signed-off-by: Holger Brunck CC: Valentin Longchamp CC: Stefan Roese Reviewed-by: Stefan Roese --- board/keymile/km_arm/Kconfig | 12 ++++++++ board/keymile/km_arm/MAINTAINERS | 1 + board/keymile/km_arm/fpga_config.c | 15 ++++++++-- configs/kmsuse2_defconfig | 58 ++++++++++++++++++++++++++++++++++++++ include/configs/km_kirkwood.h | 8 ++++++ scripts/config_whitelist.txt | 1 + 6 files changed, 93 insertions(+), 2 deletions(-) create mode 100644 configs/kmsuse2_defconfig diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig index be6b162815..4b21db8573 100644 --- a/board/keymile/km_arm/Kconfig +++ b/board/keymile/km_arm/Kconfig @@ -7,6 +7,18 @@ config KM_FPGA_CONFIG help Include capability to change FPGA configuration. +config KM_FPGA_FORCE_CONFIG + bool "FPGA reconfiguration" + default n + help + If yes we force to reconfigure the FPGA always + +config KM_FPGA_NO_RESET + bool "FPGA skip reset" + default n + help + If yes we skip triggering a reset of the FPGA + config KM_ENV_IS_IN_SPI_NOR bool "Environment in SPI NOR" default n diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 17926017c3..538f90f48b 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -9,4 +9,5 @@ F: configs/km_kirkwood_pci_defconfig F: configs/kmcoge5un_defconfig F: configs/kmnusa_defconfig F: configs/kmsugp1_defconfig +F: configs/kmsuse2_defconfig F: configs/kmsuv31_defconfig diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 051e167fd5..99bea009fa 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -82,6 +82,7 @@ static int boco_set_bits(u8 reg, u8 flags) #define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20 +#ifndef CONFIG_KM_FPGA_FORCE_CONFIG static int fpga_done(void) { int ret = 0; @@ -100,13 +101,16 @@ static int fpga_done(void) return regval & FPGA_DONE ? 1 : 0; } +#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */ -int skip; +static int skip; int trigger_fpga_config(void) { int ret = 0; + skip = 0; +#ifndef CONFIG_KM_FPGA_FORCE_CONFIG /* if the FPGA is already configured, we do not want to * reconfigure it */ skip = 0; @@ -115,6 +119,7 @@ int trigger_fpga_config(void) skip = 1; return 0; } +#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */ if (check_boco2()) { /* we have a BOCO2, this has to be triggered here */ @@ -188,7 +193,13 @@ int wait_for_fpga_config(void) return 0; } -#if defined(KM_PCIE_RESET_MPP7) +#if defined(CONFIG_KM_FPGA_NO_RESET) +int fpga_reset(void) +{ + /* no dedicated reset pin for FPGA */ + return 0; +} +#elif defined(KM_PCIE_RESET_MPP7) #define KM_PEX_RST_GPIO_PIN 7 int fpga_reset(void) diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig new file mode 100644 index 0000000000..e6726ebd0c --- /dev/null +++ b/configs/kmsuse2_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_KIRKWOOD=y +CONFIG_SYS_TEXT_BASE=0x07d00000 +CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_KM_FPGA_CONFIG=y +CONFIG_KM_FPGA_FORCE_CONFIG=y +CONFIG_KM_FPGA_NO_RESET=y +CONFIG_KM_ENV_IS_IN_SPI_NOR=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IDENT_STRING="\nABB SUSE2" +CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2" +CONFIG_MISC_INIT_R=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_NAND=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xD0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_RAM=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SF_DEFAULT_SPEED=8100000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_MVGBE=y +CONFIG_MII=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_BCH=y diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 064097a631..ea24964f54 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -65,6 +65,14 @@ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + +/* KM_SUSE2 */ +#elif defined(CONFIG_KM_SUSE2) +#define CONFIG_HOSTNAME "kmsuse2" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE #else #error ("Board unsupported") #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index aa809501d1..63e070868d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -940,6 +940,7 @@ CONFIG_KM_NEW_ENV CONFIG_KM_NUSA CONFIG_KM_ROOTFSSIZE CONFIG_KM_SUGP1 +CONFIG_KM_SUSE2 CONFIG_KM_SUV31 CONFIG_KM_UBI_LINUX_MTD CONFIG_KM_UBI_PARTITION_NAME_APP -- cgit From 95e3ce6a7fa9a6e0de598ce0b6597fddfb300faf Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Mon, 13 Jan 2020 15:34:02 +0100 Subject: arm/km: remove unmaintained board SUGP1 This target is out of maintenance and can be removed. Signed-off-by: Holger Brunck CC: Valentin Longchamp CC: Stefan Roese Reviewed-by: Stefan Roese --- board/keymile/km_arm/MAINTAINERS | 1 - board/keymile/km_arm/fpga_config.c | 23 --------------- board/keymile/km_arm/km_arm.c | 4 --- configs/kmsugp1_defconfig | 57 -------------------------------------- include/configs/km_kirkwood.h | 9 ++---- scripts/config_whitelist.txt | 1 - 6 files changed, 2 insertions(+), 93 deletions(-) delete mode 100644 configs/kmsugp1_defconfig diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 538f90f48b..45c0b5651d 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -8,6 +8,5 @@ F: configs/km_kirkwood_128m16_defconfig F: configs/km_kirkwood_pci_defconfig F: configs/kmcoge5un_defconfig F: configs/kmnusa_defconfig -F: configs/kmsugp1_defconfig F: configs/kmsuse2_defconfig F: configs/kmsuv31_defconfig diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 99bea009fa..8bb0470bc3 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -199,29 +199,6 @@ int fpga_reset(void) /* no dedicated reset pin for FPGA */ return 0; } -#elif defined(KM_PCIE_RESET_MPP7) - -#define KM_PEX_RST_GPIO_PIN 7 -int fpga_reset(void) -{ - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - printf("PCIe reset through GPIO7: "); - /* apply PCIe reset via GPIO */ - kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1); - kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1); - kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0); - udelay(1000*10); - kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1); - - printf(" done\n"); - - return 0; -} - #else #define PRST1 0x4 diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 473acfca68..7d191ab860 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -69,11 +69,7 @@ static const u32 kwmpp_config[] = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, -#if defined(KM_PCIE_RESET_MPP7) - MPP7_GPO, -#else MPP7_PEX_RST_OUTn, -#endif #if defined(CONFIG_SYS_I2C_SOFT) MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig deleted file mode 100644 index f740ff2f3a..0000000000 --- a/configs/kmsugp1_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_PIGGY4_88E6352=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_IDENT_STRING="\nKeymile SUGP1" -CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MV88E6352_SWITCH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index ea24964f54..37f9aa0058 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -38,15 +38,10 @@ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_DISABLE_PCIE -/* KM_NUSA / KM_SUGP1 */ -#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) -# if defined(CONFIG_KM_NUSA) #define CONFIG_HOSTNAME "kmnusa" -# elif defined(CONFIG_KM_SUGP1) -#define CONFIG_HOSTNAME "kmsugp1" -#define KM_PCIE_RESET_MPP7 -#endif #undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 63e070868d..c110c71f2a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -939,7 +939,6 @@ CONFIG_KM_KIRKWOOD_PCI CONFIG_KM_NEW_ENV CONFIG_KM_NUSA CONFIG_KM_ROOTFSSIZE -CONFIG_KM_SUGP1 CONFIG_KM_SUSE2 CONFIG_KM_SUV31 CONFIG_KM_UBI_LINUX_MTD -- cgit From b0405e08f4a448d82088c94d15dde40935e01b15 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Mon, 13 Jan 2020 15:34:03 +0100 Subject: arm/km: remove unmaintained board kmsuv31 This target is out of maintenance and can be removed. Signed-off-by: Holger Brunck CC: Valentin Longchamp CC: Stefan Roese Reviewed-by: Stefan Roese --- board/keymile/km_arm/MAINTAINERS | 1 - configs/kmsuv31_defconfig | 55 ---------------------------------------- include/configs/km_kirkwood.h | 8 ------ scripts/config_whitelist.txt | 1 - 4 files changed, 65 deletions(-) delete mode 100644 configs/kmsuv31_defconfig diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 45c0b5651d..3eeb509060 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -9,4 +9,3 @@ F: configs/km_kirkwood_pci_defconfig F: configs/kmcoge5un_defconfig F: configs/kmnusa_defconfig F: configs/kmsuse2_defconfig -F: configs/kmsuv31_defconfig diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig deleted file mode 100644 index 977030a1a3..0000000000 --- a/configs/kmsuv31_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_IDENT_STRING="\nKeymile SUV31" -CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 37f9aa0058..82c2a12922 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -53,14 +53,6 @@ #define CONFIG_HOSTNAME "kmcoge5un" #define CONFIG_KM_DISABLE_PCIE -/* KM_SUV31 */ -#elif defined(CONFIG_KM_SUV31) -#define CONFIG_HOSTNAME "kmsuv31" -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE - /* KM_SUSE2 */ #elif defined(CONFIG_KM_SUSE2) #define CONFIG_HOSTNAME "kmsuse2" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c110c71f2a..cbc95029ff 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -940,7 +940,6 @@ CONFIG_KM_NEW_ENV CONFIG_KM_NUSA CONFIG_KM_ROOTFSSIZE CONFIG_KM_SUSE2 -CONFIG_KM_SUV31 CONFIG_KM_UBI_LINUX_MTD CONFIG_KM_UBI_PARTITION_NAME_APP CONFIG_KM_UBI_PARTITION_NAME_BOOT -- cgit From c7c0233235542db090bbe0b75ee6ae0dbcc43bac Mon Sep 17 00:00:00 2001 From: Dhananjay Phadke Date: Tue, 14 Jan 2020 17:41:41 -0800 Subject: qemu-arm: set CONFIG_SYS_BOOTM_LEN to SZ_64M FIT image contents can be larger than default bootm limit 8M with initrd. Raise limit to 64MB which is commonly used elsewhere. Signed-off-by: Dhananjay Phadke Reviewed-by: Bin Meng --- include/configs/qemu-arm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index fb599c9510..1ef75a8783 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -17,6 +17,8 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) #define CONFIG_SYS_MALLOC_LEN SZ_16M +#define CONFIG_SYS_BOOTM_LEN SZ_64M + /* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */ #define CONFIG_SYS_HZ 1000 -- cgit From a9d1c0e2bc3fced595b742d90e65c744c55616b3 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 16 Jan 2020 20:36:58 +0100 Subject: disk: part: rename parameter of lba512_muldiv() div_by is a misleading parameter name, when we are doing >> div_by. Rename it to right_shift. Reported-by: Simon Glass Signed-off-by: Heinrich Schuchardt --- disk/part.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/disk/part.c b/disk/part.c index 8982ef3bae..4cc2fc19f7 100644 --- a/disk/part.c +++ b/disk/part.c @@ -104,17 +104,18 @@ typedef lbaint_t lba512_t; #endif /* - * Overflowless variant of (block_count * mul_by / 2**div_by) - * when div_by > mul_by + * Overflowless variant of (block_count * mul_by / 2**right_shift) + * when 2**right_shift > mul_by */ -static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, int div_by) +static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, + int right_shift) { lba512_t bc_quot, bc_rem; /* x * m / d == x / d * m + (x % d) * m / d */ - bc_quot = block_count >> div_by; - bc_rem = block_count - (bc_quot << div_by); - return bc_quot * mul_by + ((bc_rem * mul_by) >> div_by); + bc_quot = block_count >> right_shift; + bc_rem = block_count - (bc_quot << right_shift); + return bc_quot * mul_by + ((bc_rem * mul_by) >> right_shift); } void dev_print (struct blk_desc *dev_desc) -- cgit