From daebd48fe849552ce9de9d6311f525134b138974 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Jun 2018 13:02:27 -0600 Subject: Revert "tegra: Introduce SRAM repair on tegra124" This reverts commit 701b7b1d2cf657d435d2bd6caf43d0247d37220d. It will be immediately replaced by a different implementation that is more complete and runs are more targetted times. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra124/flow.h | 12 ------------ arch/arm/mach-tegra/powergate.c | 20 +------------------- 2 files changed, 1 insertion(+), 31 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index a54425692b..2b330dc9e1 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -25,12 +25,6 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ - u32 flow_dbg_sel; /* offset 0x44 */ - u32 flow_dbg_cnt0; /* offset 0x48 */ - u32 flow_dbg_cnt1; /* offset 0x4c */ - u32 flow_dbg_qual; /* offset 0x50 */ - u32 flow_ctlr_spare; /* offset 0x54 */ - u32 ram_repair_cluster1;/* offset 0x58 */ }; /* HALT_COP_EVENTS_0, 0x04 */ @@ -48,10 +42,4 @@ struct flow_ctlr { #define CSR_WAIT_WFI_SHIFT 8 #define CSR_PWR_OFF_STS (1 << 16) -/* RAM_REPAIR, 0x40, 0x58 */ -enum { - RAM_REPAIR_REQ = 0x1 << 0, - RAM_REPAIR_STS = 0x1 << 1, -}; - #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index d32d559f13..e45f0961b2 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -8,7 +8,7 @@ #include #include -#include + #include #include @@ -74,29 +74,11 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) return 0; } -static void tegra_powergate_ram_repair(void) -{ -#ifdef CONFIG_TEGRA124 - struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; - - /* Request RAM repair for cluster 0 and wait until complete */ - setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); - while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS)) - ; - - /* Same for cluster 1 */ - setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); - while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) - ; -#endif -} - int tegra_powergate_sequence_power_up(enum tegra_powergate id, enum periph_id periph) { int err; - tegra_powergate_ram_repair(); reset_set_enable(periph, 1); err = tegra_powergate_power_on(id); -- cgit From 3cc7942a4ae5d005ae2812a53d912dbab0e23760 Mon Sep 17 00:00:00 2001 From: Bibek Basu Date: Fri, 22 Jun 2018 13:02:28 -0600 Subject: ARM: tegra: implement RAM repair RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active). RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state. start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots. Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below. Signed-off-by: Bibek Basu Signed-off-by: Sandipan Patra Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra124/flow.h | 10 ++++++++ arch/arm/mach-tegra/tegra124/cpu.c | 42 +++++++++++++++++++++++++++++-- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index 2b330dc9e1..62947bf99c 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -25,6 +25,12 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctrl_spare; /* offset 0x54 */ + u32 ram_repair_cluster1;/* offset 0x58 */ }; /* HALT_COP_EVENTS_0, 0x04 */ @@ -42,4 +48,8 @@ struct flow_ctlr { #define CSR_WAIT_WFI_SHIFT 8 #define CSR_PWR_OFF_STS (1 << 16) +#define RAM_REPAIR_REQ BIT(0) +#define RAM_REPAIR_STS BIT(1) +#define RAM_REPAIR_BYPASS_EN BIT(2) + #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 204d6e9539..992c0beb04 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -104,6 +104,43 @@ static void remove_cpu_resets(void) writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); } +static void tegra124_ram_repair(void) +{ + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + u32 ram_repair_timeout; /*usec*/ + u32 val; + + /* + * Request the Flow Controller perform RAM repair whenever it turns on + * a power rail that requires RAM repair. + */ + clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN); + + /* Request SW trigerred RAM repair by setting req bit */ + /* cluster 0 */ + setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + /* Wait for completion (status == 0) */ + ram_repair_timeout = 500; + do { + udelay(1); + val = readl(&flow->ram_repair); + } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--); + if (!ram_repair_timeout) + debug("Ram Repair cluster0 failed\n"); + + /* cluster 1 */ + setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + /* Wait for completion (status == 0) */ + ram_repair_timeout = 500; + do { + udelay(1); + val = readl(&flow->ram_repair_cluster1); + } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--); + + if (!ram_repair_timeout) + debug("Ram Repair cluster1 failed\n"); +} + /** * Tegra124 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster @@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector) &pmc->pmc_pwrgate_timer_mult); enable_cpu_power_rail(); + powerup_cpus(); + tegra124_ram_repair(); enable_cpu_clocks(); clock_enable_coresight(1); - remove_cpu_resets(); writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); - powerup_cpus(); + remove_cpu_resets(); debug("%s exit, should continue @ reset_vector\n", __func__); } -- cgit From 3e3b2b47766ac9a9ad4bf30ea0015b8a2b5f1802 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Jun 2018 13:03:16 -0600 Subject: ARM: define MON_MODE Add a MON_MODE define for ARM's monitor mode. This can be used later by a secure monitor to avoid hard-coding mode IDs. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/proc-armv/ptrace.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 71df5a9e25..183b00a087 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -37,6 +37,7 @@ struct pt_regs { #define FIQ_MODE 0x11 #define IRQ_MODE 0x12 #define SVC_MODE 0x13 +#define MON_MODE 0x16 #define ABT_MODE 0x17 #define HYP_MODE 0x1a #define UND_MODE 0x1b -- cgit From 326bd726d022f2be57ce9cd86f41130a0097beb6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Jun 2018 13:03:17 -0600 Subject: ARM: PSCI: Support PSCI v0.2 Enhance the PSCI DT editing code to allow setting a PSCI v0.2 compatible value in the DT. The CONFIG_ option is added to the whitelist to match the existing PSCI_1_0 option. While not adding new options to Kconfig isn't ideal, I figure it's better to keep related options together. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/lib/psci-dt.c | 2 ++ scripts/config_whitelist.txt | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 825fe1eefb..348df893b7 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -67,6 +67,8 @@ init_psci_node: psci_ver = sec_firmware_support_psci_version(); #elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI) psci_ver = ARM_PSCI_VER_1_0; +#elif defined(CONFIG_ARMV7_PSCI_0_2) + psci_ver = ARM_PSCI_VER_0_2; #endif if (psci_ver >= ARM_PSCI_VER_1_0) { tmp = fdt_setprop_string(fdt, nodeoff, diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 1aebe17421..7ced4099f2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -51,6 +51,7 @@ CONFIG_ARMADA100 CONFIG_ARMADA100_FEC CONFIG_ARMADA168 CONFIG_ARMADA_39X +CONFIG_ARMV7_PSCI_0_2 CONFIG_ARMV7_PSCI_1_0 CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE -- cgit From 74c69cdcc01694b9c08194f2c0fc49f53e766810 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Jun 2018 13:03:18 -0600 Subject: ARM: PSCI: Enable the PSCI node When fixing up the DT to report PSCI support, explicitly enable the node. DTs may ship with the node disabled in case a PSCI implementation is not present, and expect any PSCI implementation to enable the node if they are actually present. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/lib/psci-dt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 348df893b7..246f3c7cb8 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -116,6 +116,10 @@ init_psci_node: if (tmp) return tmp; + tmp = fdt_setprop_string(fdt, nodeoff, "status", "okay"); + if (tmp) + return tmp; + #endif return 0; } -- cgit From 6e584e633d1072a37493aed3314065b57ef9d991 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Jun 2018 13:03:19 -0600 Subject: ARM: tegra: avoid using secure carveout RAM If a secure carveout exists, U-Boot cannot use that memory. Fix carveout_size() to reflect this, and hence transitively fix usable_ram_size_below_4g() and board_get_usable_ram_top(). This change ensures that when U-Boot copies the secure monitor code to install it, the copy target is not in-use for U-Boot code/data. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/mach-tegra/board2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 25da771607..5ecadf705e 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -249,6 +249,10 @@ static ulong carveout_size(void) { #ifdef CONFIG_ARM64 return SZ_512M; +#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE) + // BASE+SIZE might not == 4GB. If so, we want the carveout to cover + // from BASE to 4GB, not BASE to BASE+SIZE. + return (0 - CONFIG_ARMV7_SECURE_BASE); #else return 0; #endif -- cgit From 2eea1269166fd3dccc319629e612edddcd650803 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 26 Jul 2018 13:14:15 -0700 Subject: tegra: beaver/apalis: Fix DTC warning Fix warning when compiling tegra30-beaver/-apalis.dts with latest DTC: "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property" Signed-off-by: Tom Warren --- arch/arm/dts/tegra30-apalis.dts | 3 --- arch/arm/dts/tegra30-beaver.dts | 3 --- 2 files changed, 6 deletions(-) diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 0852d8dc53..1a9ce2720a 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -119,9 +119,6 @@ vccio-supply = <&sys_3v3_reg>; regulators { - #address-cells = <1>; - #size-cells = <0>; - /* SW1: +V1.35_VDDIO_DDR */ vdd1_reg: vdd1 { regulator-name = "vddio_ddr_1v35"; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index c1a15bb4b3..f5fbbe849e 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -102,9 +102,6 @@ vccio-supply = <&vdd_5v_in_reg>; regulators { - #address-cells = <1>; - #size-cells = <0>; - vdd1_reg: vdd1 { regulator-name = "vddio_ddr_1v2"; regulator-min-microvolt = <1200000>; -- cgit