From e74244c5a1c8bcea9b047217277dcd3235a285f4 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Mon, 10 May 2010 15:23:20 -0700 Subject: Removal of checkboard from spl bootstrap build for SIMPC8313 This patch removes the checkboard function from the build of the 4k bootstrap section for the SIMPC8313 as it is not needed in the spl build. This will allow > 100 bytes of extra room for other uses. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- board/sheldon/simpc8313/simpc8313.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index 0235545ae4..cb30b48859 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -33,13 +33,13 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_NAND_SPL int checkboard(void) { puts("Board: Sheldon Instruments SIMPC8313\n"); return 0; } -#ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, -- cgit From a4bfc4cc466473b97c7fe84bdf261b2935887e3f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 14 May 2010 13:18:54 -0500 Subject: mpc83xx: fix NAND bootstrap too big error commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable port-mapped access" inadvertently broke 83xx nand boards by converting NS16550_init to use io accessors, which expanded the size of the generated code. this patch fixes the problem by removing icache functions from the nand builds, which somewhat follows commit 1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache in core initialization to improve u-boot boot time" Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index a7c80792de..1b3d618f49 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -739,6 +739,7 @@ setup_bats: * Note: requires that all cache bits in * HID0 are in the low half word. */ +#ifndef CONFIG_NAND_SPL .globl icache_enable icache_enable: mfspr r3, HID0 @@ -767,6 +768,7 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr +#endif /* !CONFIG_NAND_SPL */ .globl dcache_enable dcache_enable: -- cgit From b1e1a42bb1ea2f0ddaaea7f4c9d67c98ab38709e Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Fri, 14 May 2010 16:27:48 -0700 Subject: Fix SICRL setting in SIMPC8313 This patch sets the SICRL_LBC bits in SICRL to change the function of the associated pins to GPIO functionality. Signed-off-by: Ron Madrid --- include/configs/SIMPC8313.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 1a17323a51..9104f1ad36 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -418,7 +418,8 @@ | SICRH_ETSEC2_G \ | SICRH_TSOBI1 \ | SICRH_TSOBI2 ) -#define CONFIG_SYS_SICRL (SICRL_USBDR \ +#define CONFIG_SYS_SICRL ( SICRL_LBC \ + | SICRL_USBDR \ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 -- cgit