From e88f421e7a65e5bd0c6131e5202d710e73dd4aae Mon Sep 17 00:00:00 2001 From: Zang Roy-R61911 Date: Thu, 28 Nov 2013 13:23:37 +0800 Subject: T4240: Address T4240/T4160 Rev2.0 DDR clock change MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang Signed-off-by: Shaohui Xie Acked-by: York Sun --- arch/powerpc/cpu/mpc85xx/speed.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a194f9..46ae80c4d8 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; else -- cgit