From f8cf3d1ebdf7622f65c4eeba9eae1ed04982de12 Mon Sep 17 00:00:00 2001 From: Igor Guryanov Date: Wed, 24 Dec 2014 16:07:07 +0300 Subject: arc: check caches existence before use Some cache operations ({i|d}cache_{enable|disable|status} or flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF is set. This is required for force disable of caches on early boot. What if something was executed before U-boot and enabled caches (low-level bootloaders, previously run kernel etc.)? But if CPU doesn't really have caches any attempt to access cache-related AUX registers triggers instruction error exception. So for convenience we'll try to avoid exceptions by checking if CPU actually has caches (we check separately data and instruction cache existence) at all. Signed-off-by: Alexey Brodkin Signed-off-by: Igor Guryanov --- arch/arc/include/asm/arcregs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 5d48d11bab..8ace87fa0f 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -24,6 +24,7 @@ #if (CONFIG_ARC_MMU_VER > 2) #define ARC_AUX_IC_PTAG 0x1E #endif +#define ARC_BCR_IC_BUILD 0x77 /* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ @@ -42,6 +43,7 @@ #if (CONFIG_ARC_MMU_VER > 2) #define ARC_AUX_DC_PTAG 0x5C #endif +#define ARC_BCR_DC_BUILD 0x72 #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ -- cgit From 20a58ac0d8e09d0bf1a74c6b68fea22784512b51 Mon Sep 17 00:00:00 2001 From: Igor Guryanov Date: Wed, 24 Dec 2014 17:17:11 +0300 Subject: arc: introduce separate section for interrupt vector table Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin Signed-off-by: Igor Guryanov --- arch/arc/include/asm/sections.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 18484a17f2..2a7a98713d 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -10,5 +10,7 @@ #include extern ulong __text_end; +extern ulong __ivt_start; +extern ulong __ivt_end; #endif /* __ASM_ARC_SECTIONS_H */ -- cgit From 1c91a3d9790c6d8f4bcb0d896936672509a1439d Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Fri, 26 Dec 2014 19:36:30 +0300 Subject: arc: relocate - minor refactoring and clean-up * use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/sections.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 2a7a98713d..b8f2a859fd 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -12,5 +12,6 @@ extern ulong __text_end; extern ulong __ivt_start; extern ulong __ivt_end; +extern ulong __image_copy_start; #endif /* __ASM_ARC_SECTIONS_H */ -- cgit