From f8cf3d1ebdf7622f65c4eeba9eae1ed04982de12 Mon Sep 17 00:00:00 2001 From: Igor Guryanov Date: Wed, 24 Dec 2014 16:07:07 +0300 Subject: arc: check caches existence before use Some cache operations ({i|d}cache_{enable|disable|status} or flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF is set. This is required for force disable of caches on early boot. What if something was executed before U-boot and enabled caches (low-level bootloaders, previously run kernel etc.)? But if CPU doesn't really have caches any attempt to access cache-related AUX registers triggers instruction error exception. So for convenience we'll try to avoid exceptions by checking if CPU actually has caches (we check separately data and instruction cache existence) at all. Signed-off-by: Alexey Brodkin Signed-off-by: Igor Guryanov --- arch/arc/include/asm/arcregs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 5d48d11bab..8ace87fa0f 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -24,6 +24,7 @@ #if (CONFIG_ARC_MMU_VER > 2) #define ARC_AUX_IC_PTAG 0x1E #endif +#define ARC_BCR_IC_BUILD 0x77 /* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ @@ -42,6 +43,7 @@ #if (CONFIG_ARC_MMU_VER > 2) #define ARC_AUX_DC_PTAG 0x5C #endif +#define ARC_BCR_DC_BUILD 0x72 #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ -- cgit From 20a58ac0d8e09d0bf1a74c6b68fea22784512b51 Mon Sep 17 00:00:00 2001 From: Igor Guryanov Date: Wed, 24 Dec 2014 17:17:11 +0300 Subject: arc: introduce separate section for interrupt vector table Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin Signed-off-by: Igor Guryanov --- arch/arc/include/asm/sections.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 18484a17f2..2a7a98713d 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -10,5 +10,7 @@ #include extern ulong __text_end; +extern ulong __ivt_start; +extern ulong __ivt_end; #endif /* __ASM_ARC_SECTIONS_H */ -- cgit From 1c91a3d9790c6d8f4bcb0d896936672509a1439d Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Fri, 26 Dec 2014 19:36:30 +0300 Subject: arc: relocate - minor refactoring and clean-up * use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/sections.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 2a7a98713d..b8f2a859fd 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -12,5 +12,6 @@ extern ulong __text_end; extern ulong __ivt_start; extern ulong __ivt_end; +extern ulong __image_copy_start; #endif /* __ASM_ARC_SECTIONS_H */ -- cgit From 812980bdd6c9112014f3946d1cb2728a2121ba34 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:11 +0300 Subject: arc: add more flavours of ARC700 series CPU Now we may select a particular version of ARC700: * ARC750D or * ARC770D It allows more flexible (or more fine tuned) configuration of U-Boot. Before that change we relied on minimal configuration but now we may use specific features of each CPU. Moreover allows us to escape manual selection of options that exist in both CPUs but may have say different version like MMUv2 in ARC750D vs MMUv3 in ARC770D. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/arcregs.h | 2 ++ arch/arc/include/asm/cache.h | 6 ++++++ 2 files changed, 8 insertions(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 8ace87fa0f..31627e65b9 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARC_ARCREGS_H #define _ASM_ARC_ARCREGS_H +#include + /* * ARC architecture has additional address space - auxiliary registers. * These registers are mostly used for configuration purposes. diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 16e7568ef0..368d1f016e 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -20,4 +20,10 @@ #define ARCH_DMA_MINALIGN 128 #endif +#if defined(CONFIG_ARC_MMU_V2) +#define CONFIG_ARC_MMU_VER 2 +#elif defined(CONFIG_ARC_MMU_V3) +#define CONFIG_ARC_MMU_VER 3 +#endif + #endif /* __ASM_ARC_CACHE_H */ -- cgit From 5ff40f3d4226d45c78f3bb9db276f6685b24a89a Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:12 +0300 Subject: arc: define and use PTAG AUX regs for MMUv3 only DC_PTAG and IC_PTAG registers only exist in MMUv3. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/arcregs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 31627e65b9..6a36a81c0f 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -23,7 +23,7 @@ #define ARC_AUX_IC_IVIC 0x10 #define ARC_AUX_IC_CTRL 0x11 #define ARC_AUX_IC_IVIL 0x19 -#if (CONFIG_ARC_MMU_VER > 2) +#if (CONFIG_ARC_MMU_VER == 3) #define ARC_AUX_IC_PTAG 0x1E #endif #define ARC_BCR_IC_BUILD 0x77 @@ -42,7 +42,7 @@ #define ARC_AUX_DC_IVDL 0x4A #define ARC_AUX_DC_FLSH 0x4B #define ARC_AUX_DC_FLDL 0x4C -#if (CONFIG_ARC_MMU_VER > 2) +#if (CONFIG_ARC_MMU_VER == 3) #define ARC_AUX_DC_PTAG 0x5C #endif #define ARC_BCR_DC_BUILD 0x72 -- cgit From 205e7a7b77726abeff57576e2ecf2c6d4dc07ccf Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:13 +0300 Subject: arc: select cache settings via menuconfig This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/cache.h | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 368d1f016e..2725961221 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,15 +9,12 @@ #include -/* - * The current upper bound for ARC L1 data cache line sizes is 128 bytes. - * We use that value for aligning DMA buffers unless the board config has - * specified an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#ifdef CONFIG_ARC_CACHE_LINE_SHIFT +#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT) +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #else -#define ARCH_DMA_MINALIGN 128 +/* Satisfy users of ARCH_DMA_MINALIGN */ +#define ARCH_DMA_MINALIGN 128 #endif #if defined(CONFIG_ARC_MMU_V2) -- cgit From 6eb651ad29636682067f76de4f40c45119269f8b Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:15 +0300 Subject: arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.h There're no other options for ARC except "generic board" so ther's no point to define CONFIG_SYS_GENERIC_BOARD per board. We now have it set fo all ARC boards. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h index e5be078c19..c1e9b44239 100644 --- a/arch/arc/include/asm/config.h +++ b/arch/arc/include/asm/config.h @@ -7,6 +7,7 @@ #ifndef __ASM_ARC_CONFIG_H_ #define __ASM_ARC_CONFIG_H_ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_SYS_BOOT_RAMDISK_HIGH -- cgit From a1dbe57d2d45d311e402c357831bbf5c5157a32c Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:17 +0300 Subject: arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.h Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards so there's no sense in separate per-board definitions. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h index c1e9b44239..b4e9099fb1 100644 --- a/arch/arc/include/asm/config.h +++ b/arch/arc/include/asm/config.h @@ -10,6 +10,7 @@ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_SYS_BOOT_RAMDISK_HIGH +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_LMB -- cgit