From bd91508b50ade5c73b3749bf4e5ede31d2da7ef8 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 8 Jun 2016 07:57:19 +0300 Subject: arc/cache: really do invalidate_dcache_all() even if IOC exists invalidate_dcache_all() could be used in different use-cases and what is especially important most of those cases won't be related to DMAed data to or from peripherals, i.e. we'll be doing invalidation of data used purely by CPU cores. Given that IOC engine only snoops data that goes through DMA we need to care ourselves about data used only by CPU cores and so remove dependency on IOC from invalidate_dcache_all() and always do real invalidation. Signed-off-by: Alexey Brodkin --- arch/arc/lib/cache.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arc/lib/cache.c') diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index d1fb661537..a27499e027 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -417,13 +417,10 @@ void flush_cache(unsigned long start, unsigned long size) void invalidate_dcache_all(void) { -#ifdef CONFIG_ISA_ARCV2 - if (!ioc_exists) -#endif - __dc_entire_op(OP_INV); + __dc_entire_op(OP_INV); #ifdef CONFIG_ISA_ARCV2 - if (slc_exists && !ioc_exists) + if (slc_exists) __slc_entire_op(OP_INV); #endif } -- cgit From a4a43fcf9cca1ebd3d26f9a01b923b7393d69c54 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 8 Jun 2016 08:04:03 +0300 Subject: arc/cache: Flush & invalidate all caches right before enabling IOC According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin --- arch/arc/lib/cache.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arc/lib/cache.c') diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index a27499e027..b6ec83112c 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -209,6 +209,9 @@ void cache_init(void) read_decode_cache_bcr_arcv2(); if (ioc_exists) { + flush_dcache_all(); + invalidate_dcache_all(); + /* IO coherency base - 0x8z */ write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ -- cgit