From fe3eb7a88720fc33d92ed712c56c62cfcdffc0ca Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Fri, 8 Jun 2018 17:58:23 +0300 Subject: GPIO: CREG: improve flexibility of hsdk-creg-gpio driver CREG GPIO is a driver for weird soc-specific output ports, which are controlled by some fields in memory mapped register. Example: 31 9 7 5 0 < bit number | | | | | [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register ^ ^ | | write 0x2 == set output to "1" (activate) write 0x3 == set output to "0" (deactivate) As of tooday we only support fixed (hardcoded) bit per gpio line, activate / deactivatei and shift values. Fix that by read them from device tree to be able to use this driver for other boards. Remove "hsdk" prefix from compatible string as this driver can be used with different boards like HSDK, AXS101, AXS103, etc. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- arch/arc/dts/hsdk.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arc') diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index 264512877e..e41e4ce84b 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -101,11 +101,16 @@ }; cs_gpio: gpio@f00014b0 { - compatible = "snps,hsdk-creg-gpio"; + compatible = "snps,creg-gpio"; reg = <0xf00014b0 0x4>; gpio-controller; #gpio-cells = <1>; gpio-bank-name = "hsdk-spi-cs"; gpio-count = <1>; + gpio-first-shift = <0>; + gpio-bit-per-line = <2>; + gpio-activate-val = <2>; + gpio-deactivate-val = <3>; + gpio-default-val = <1>; }; }; -- cgit From cdfe6913c113ced9a0aa0a7dc48d037046c980e3 Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Fri, 8 Jun 2018 18:52:14 +0300 Subject: AXS10x: add spi flash support AXS10x boards have n25q512 spi flash IC, so add corresponding nodes to device tree and enaple corresponding options in defconfig. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- arch/arc/dts/axs10x_mb.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arc') diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index 3855a34dc2..dfc03810ca 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -4,6 +4,10 @@ */ / { + aliases { + spi0 = &spi0; + }; + axs10x_mb@e0000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -56,5 +60,35 @@ reg-shift = <2>; reg-io-width = <4>; }; + + spi0: spi@0 { + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <4000000>; + clocks = <&apbclk>; + clock-names = "spi_clk"; + cs-gpio = <&cs_gpio 0>; + spi_flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <4000000>; + }; + }; + + cs_gpio: gpio@11218 { + compatible = "snps,creg-gpio"; + reg = <0x11218 0x4>; + gpio-controller; + #gpio-cells = <1>; + gpio-bank-name = "axs-spi-cs"; + gpio-count = <1>; + gpio-first-shift = <0>; + gpio-bit-per-line = <2>; + gpio-activate-val = <1>; + gpio-deactivate-val = <3>; + gpio-default-val = <1>; + }; }; }; -- cgit From 8f590063ba635264303b1713c421df331743fd46 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Sun, 29 Jul 2018 09:47:52 +0300 Subject: ARC: Enable unaligned access in hardware if compiler uses it Even if ARC core might handle unaligned access to data this hardware feature by default is disabled. But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores. Which leads to quite strange and fatal run-time failures like the one below if HW is not configured properly: | hsdk# sf probe | Misaligned data access exception @ 0xbff794d4 | ECR: 0x000d0000 | RET: 0xbff794d4 | BLINK: 0xbff79644 | STAT32: 0x00000800 | GP: 0x1003e000 r25: 0xbfd58f08 | BTA: 0xbff794a4 SP: 0xbfd58cd4 FP: 0xbfd58ef0 | LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000 | r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf | r03: 0x00000000 r04: 0x00000100 r05: 0x00000000 | r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500 | r09: 0x00000000 r10: 0x00200000 r11: 0x00000000 | r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68 | r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000 | r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40 | r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000 | r24: 0xbfd59ba8 | Resetting CPU ... Now we're checking for __ARC_UNALIGNED__ define emitted by the compiler if it's going to use unaligned access and then we force-enable it in hardware too. Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/arcregs.h | 3 +++ arch/arc/lib/start.S | 9 +++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arc') diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 56ec11f789..9920d2e719 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -19,6 +19,9 @@ #define ARC_AUX_IDENTITY 0x04 #define ARC_AUX_STATUS32 0x0a +/* STATUS32 Bits Positions */ +#define STATUS_AD_BIT 19 /* Enable unaligned access */ + /* Instruction cache related auxiliary registers */ #define ARC_AUX_IC_IVIC 0x10 #define ARC_AUX_IC_CTRL 0x11 diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index e573ce7718..84959b41bd 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -61,6 +61,15 @@ ENTRY(_start) 1: #endif +#ifdef __ARC_UNALIGNED__ + /* + * Enable handling of unaligned access in the CPU as by default + * this HW feature is disabled while GCC starting from 8.1.0 + * unconditionally uses it for ARC HS cores. + */ + flag 1 << STATUS_AD_BIT +#endif + /* Establish C runtime stack and frame */ mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp -- cgit