From cf202d268b5d27b84a8c6df1d749ed3967451be4 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Thu, 20 Nov 2014 21:14:12 +0800 Subject: mx6: clock: Add thermal clock enable function Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li Signed-off-by: Nitin Garg --- arch/arm/cpu/armv7/mx6/clock.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/cpu/armv7/mx6/clock.c') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 6c9c78c11a..80b11aaf50 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -673,6 +673,36 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +static void enable_pll3(void) +{ + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + /* make sure pll3 is enabled */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } +} + +void enable_thermal_clk(void) +{ + enable_pll3(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { -- cgit From 8d29cef5887887157f54f98493440ce5c824d5cb Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Fri, 21 Nov 2014 12:47:22 +0200 Subject: arm: mx6: introduce disable_sata_clock Implement disable_sata_clock for mx6 SoCs. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/clock.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/cpu/armv7/mx6/clock.c') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 80b11aaf50..ab7ac3d703 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -596,6 +596,14 @@ int enable_sata_clock(void) ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } + +void disable_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} #endif int enable_pcie_clock(void) -- cgit