From 43037d76316db1a53be16a4c1ed97203257fa4ee Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:24 +0000 Subject: OMAP5: ADD precalculated timings for ddr3 Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b5389606b6..239ad2b07c 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -92,6 +92,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { /* Dummy registers for OMAP44xx */ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, -- cgit From 784ab7c545d25288a82216d18e2b0ca3beae470b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:25 +0000 Subject: OMAP5: EMIF: Add support for DDR3 device In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap4/hwinit.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 187e93887b..2c34e48f42 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -118,6 +118,11 @@ void do_io_settings(void) } #endif +/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + void init_omap_revision(void) { /* -- cgit From cc009defa4211aa58b3387b59d568cf8ea863ef4 Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Wed, 13 Jun 2012 05:16:40 +0000 Subject: omap4: Use a smaller M,N couple for IVA DPLL This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan --- arch/arm/cpu/armv7/omap4/clocks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c568951a91..1d92e66545 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ -- cgit From 254763822e966b6c630d78dc17018b97a50d8f6e Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Jun 2012 03:40:23 +0000 Subject: ARM: OMAP4+: Move external phy initialisations to arch specific place. The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan --- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index 239ad2b07c..b9128faa56 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -91,7 +91,6 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { }; /* Dummy registers for OMAP44xx */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { -- cgit From dbf8fb6ad1fc8b1708e0460bf3b5b7b2035badea Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Jun 2012 19:53:30 +0000 Subject: ARM: OMAP4/5: Move gpmc clocks to essential group. GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan --- arch/arm/cpu/armv7/omap4/clocks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 1d92e66545..484a96abf1 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -354,6 +354,7 @@ void enable_basic_clocks(void) }; u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_memif_emif_1_clkctrl, &prcm->cm_memif_emif_2_clkctrl, &prcm->cm_l4cfg_l4_cfg_clkctrl, @@ -452,7 +453,6 @@ void enable_non_essential_clocks(void) }; u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, -- cgit From 5e9cd44ca08a03fdf1b8271f265981bc0a038c8d Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Jun 2012 19:53:31 +0000 Subject: ARM: OMAP4/5: Move USB clocks to essential group. USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan --- arch/arm/cpu/armv7/omap4/clocks.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 484a96abf1..5bd0a88fde 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -364,9 +364,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gpio4_clkctrl, &prcm->cm_l4per_gpio5_clkctrl, &prcm->cm_l4per_gpio6_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_clksel_usb_60mhz, - &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -377,7 +374,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gptimer2_clkctrl, &prcm->cm_wkup_wdtimer2_clkctrl, &prcm->cm_l4per_uart3_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -414,6 +410,9 @@ void enable_basic_uboot_clocks(void) u32 *const clk_modules_hw_auto_essential[] = { &prcm->cm_l3init_hsusbotg_clkctrl, &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_clksel_usb_60mhz, + &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -423,6 +422,7 @@ void enable_basic_uboot_clocks(void) &prcm->cm_l4per_i2c2_clkctrl, &prcm->cm_l4per_i2c3_clkctrl, &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -457,7 +457,6 @@ void enable_non_essential_clocks(void) &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -497,7 +496,6 @@ void enable_non_essential_clocks(void) &prcm->cm_cam_fdif_clkctrl, &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; -- cgit