From 3599774eec9d06812c6124bcd0b34cebd7ec5e1c Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 23 May 2016 17:37:49 +0300 Subject: dra7xx: Enable USB_PHY3 32KHz clock DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/cpu/armv7/omap5/prcm-regs.c') diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 655e92ba27..b5f1d700fd 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_gmac = 0x4a0052a8, .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, + .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698, .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0, /* cm1.mpu */ -- cgit