From 59c651f4e2b7614e97c2fda10eeabd00529dd740 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Feb 2013 12:38:59 +0100 Subject: arm: zynq: Add SLCR support with system reset The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/cpu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/cpu/armv7/zynq/cpu.c') diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index ab615cc7d4..91618d3d8a 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -21,11 +21,13 @@ * MA 02111-1307 USA */ #include +#include inline void lowlevel_init(void) {} void reset_cpu(ulong addr) { + zynq_slcr_cpu_reset(); while (1) ; } -- cgit From 00ed34589880ca7092999ec5b92e061018d0fd0f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Feb 2013 12:42:25 +0100 Subject: arm: zynq: Add lowlevel initialization to C Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/cpu.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/zynq/cpu.c') diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 91618d3d8a..e8f4c19d49 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -21,9 +21,33 @@ * MA 02111-1307 USA */ #include +#include #include +#include -inline void lowlevel_init(void) {} +void lowlevel_init(void) +{ + zynq_slcr_unlock(); + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + + /* Device config APB, unlock the PCAP */ + writel(0x757BDF0D, &devcfg_base->unlock); + writel(0xFFFFFFFF, &devcfg_base->rom_shadow); + + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ + writel(0x1F, &slcr_base->ocm_cfg); + /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ + writel(0x0, &slcr_base->fpga_rst_ctrl); + /* TZ_DDR_RAM, Set DDR trust zone non-secure */ + writel(0xFFFFFFFF, &slcr_base->trust_zone); + /* Set urgent bits with register */ + writel(0x0, &slcr_base->ddr_urgent_sel); + /* Urgent write, ports S2/S3 */ + writel(0xC, &slcr_base->ddr_urgent); + + zynq_slcr_lock(); +} void reset_cpu(ulong addr) { -- cgit