From 18284c1d56bfe2b51484561881377489ffa86c3b Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Fri, 10 Jul 2020 19:07:31 +0200 Subject: pwm: add driver for nexell Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - Since drivers/pwm/pwm-nexell.c is an adapted version of s5p-common/pwm.c an appropriately changed version of s5p-common/pwm.c is used instead. Therefore arch/arm/mach-s5pc1xx/include/mach/pwm.h copied to arch/arm/mach-nexell/include/mach and s5p-common/Makefile changed appropriately. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch --- arch/arm/cpu/armv7/s5p-common/Makefile | 13 +++++--- arch/arm/cpu/armv7/s5p-common/pwm.c | 57 +++++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 5 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 12cf804e88..bfe02389cd 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -3,9 +3,14 @@ # Copyright (C) 2009 Samsung Electronics # Minkyu Kang -obj-y += cpu_info.o +ifdef CONFIG_ARCH_NEXELL +obj-$(CONFIG_PWM_NX) += pwm.o +obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o +else +obj-y += cpu_info.o ifndef CONFIG_SPL_BUILD -obj-y += timer.o -obj-y += sromc.o -obj-$(CONFIG_PWM) += pwm.o +obj-y += timer.o +obj-y += sromc.o +obj-$(CONFIG_PWM) += pwm.o +endif endif diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 6b9e865803..aef2e5574b 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -15,7 +15,11 @@ int pwm_enable(int pwm_id) { const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned long tcon; tcon = readl(&pwm->tcon); @@ -29,7 +33,11 @@ int pwm_enable(int pwm_id) void pwm_disable(int pwm_id) { const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned long tcon; tcon = readl(&pwm->tcon); @@ -43,14 +51,43 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) unsigned long tin_parent_rate; unsigned int div; +#if defined(CONFIG_ARCH_NEXELL) + unsigned int pre_div; + const struct s5p_timer *pwm = + (struct s5p_timer *)PHY_BASEADDR_PWM; + unsigned int val; + struct clk *clk = clk_get(CORECLK_NAME_PCLK); + + tin_parent_rate = clk_get_rate(clk); +#else tin_parent_rate = get_pwm_clk(); +#endif + +#if defined(CONFIG_ARCH_NEXELL) + writel(0, &pwm->tcfg0); + val = readl(&pwm->tcfg0); + + if (pwm_id < 2) + div = ((val >> 0) & 0xff) + 1; + else + div = ((val >> 8) & 0xff) + 1; + writel(0, &pwm->tcfg1); + val = readl(&pwm->tcfg1); + val = (val >> MUX_DIV_SHIFT(pwm_id)) & 0xF; + pre_div = (1UL << val); + + freq = tin_parent_rate / div / pre_div; + + return freq; +#else for (div = 2; div <= 16; div *= 2) { if ((tin_parent_rate / (div << 16)) < freq) return tin_parent_rate / div; } return tin_parent_rate / 16; +#endif } #define NS_IN_SEC 1000000000UL @@ -58,7 +95,11 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) int pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; @@ -84,7 +125,12 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) tin_rate = pwm_calc_tin(pwm_id, frequency); tin_ns = NS_IN_SEC / tin_rate; - tcnt = period_ns / tin_ns; + + if (IS_ENABLED(CONFIG_ARCH_NEXELL)) + /* The counter starts at zero. */ + tcnt = (period_ns / tin_ns) - 1; + else + tcnt = period_ns / tin_ns; /* Note, counters count down */ tcmp = duty_ns / tin_ns; @@ -115,7 +161,11 @@ int pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned long ticks_per_period; unsigned int offset, prescaler; @@ -148,7 +198,12 @@ int pwm_init(int pwm_id, int div, int invert) ticks_per_period = -1UL; } else { const unsigned long pwm_hz = 1000; +#if defined(CONFIG_ARCH_NEXELL) + struct clk *clk = clk_get(CORECLK_NAME_PCLK); + unsigned long timer_rate_hz = clk_get_rate(clk) / +#else unsigned long timer_rate_hz = get_pwm_clk() / +#endif ((prescaler + 1) * (1 << div)); ticks_per_period = timer_rate_hz / pwm_hz; -- cgit From d1611086e0058c0b701cd487fc9735ffcc9c6c4c Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Fri, 10 Jul 2020 19:07:37 +0200 Subject: arm: add support for SoC s5p4418 (cpu) / nanopi2 board Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - SPL not supported yet --> no spl-dir in arch/arm/cpu/armv7/s5p4418/. Appropriate line in Makefile removed. - cpu.c: '#include ' added. - arch/arm/cpu/armv7/s5p4418/u-boot.lds removed, is not required anylonger. - "obj-$(CONFIG_ARCH_NEXELL) += s5p-common/" added to arch/arm/cpu/armv7/Makefile since s5p-common/pwm.c is used instead of drivers/pwm/pwm-nexell.c. - s5p4418.dtsi: '#include "../../../include/generated/autoconf.h"' removed, is not necessary, error at out-of-tree building. '#ifdef CONFIG_CPU_NXP4330'-blocks (2x) removed. Some minor changes regarding mmc. 'u-boot,dm-pre-reloc' added to dp0 because of added DM_VIDEO support. - board/s5p4418/ renamed to board/friendlyarm/ - All s5p4418-boards except nanopi2 removed because there is no possibility to test the other boards. - Kconfig: Changes to have a structure like mach-bcm283x (RaspberryPi), e.g. "config ..." entries moved from/to other Kconfig. - "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. - nanopi2/board.c: All getenv(), getenv_ulong(), setenv() and saveenv() renamed to env_get(), env_get_ulong(), env_set() and env_save(), respectively. MACH_TYPE_S5P4418 is not defined anymore, therefore appropriate code removed (not necessary for DT-kernels). - nanopi2/onewire.c: All crc8() renamed to crc8_ow() because crc8() is already defined in lib/crc8.c (with different parameters). - dts: "nexell,s5pxx18-i2c" used instead of "i2c-gpio", i2c0 and i2c1 added. gmac-, ehci- and dwc2otg-entries removed because the appropriate functionality is not supported yet. New mmc-property "mmcboost" added. s5p4418-pinctrl.dtsi: gmac-entries removed, mmc- and i2c-entries added. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch --- arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/s5p4418/Makefile | 6 ++ arch/arm/cpu/armv7/s5p4418/cpu.c | 121 ++++++++++++++++++++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 arch/arm/cpu/armv7/s5p4418/Makefile create mode 100644 arch/arm/cpu/armv7/s5p4418/cpu.c (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 8c955d0d52..0e83e394d5 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -42,3 +42,5 @@ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_VF610) += vf610/ +obj-$(CONFIG_ARCH_S5P4418) += s5p4418/ +obj-$(CONFIG_ARCH_NEXELL) += s5p-common/ diff --git a/arch/arm/cpu/armv7/s5p4418/Makefile b/arch/arm/cpu/armv7/s5p4418/Makefile new file mode 100644 index 0000000000..321b257b6d --- /dev/null +++ b/arch/arm/cpu/armv7/s5p4418/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 Nexell +# Hyunseok, Jung + +obj-y += cpu.o diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c new file mode 100644 index 0000000000..8add9474ad --- /dev/null +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Hyunseok, Jung + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_ARCH_CPU_INIT +#error must be define the macro "CONFIG_ARCH_CPU_INIT" +#endif + +void s_init(void) +{ +} + +static void cpu_soc_init(void) +{ + /* + * NOTE> ALIVE Power Gate must enable for Alive register access. + * must be clear wfi jump address + */ + writel(1, ALIVEPWRGATEREG); + writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT); + + /* write 0xf0 on alive scratchpad reg for boot success check */ + writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET)); + + /* set l2 cache tieoff */ + nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1); + nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); +} + +#ifdef CONFIG_PL011_SERIAL +static void serial_device_init(void) +{ + char dev[10]; + int id; + + sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX); + id = RESET_ID_UART0 + CONFIG_CONS_INDEX; + + struct clk *clk = clk_get((const char *)dev); + + /* reset control: Low active ___|--- */ + nx_rstcon_setrst(id, RSTCON_ASSERT); + udelay(10); + nx_rstcon_setrst(id, RSTCON_NEGATE); + udelay(10); + + /* set clock */ + clk_disable(clk); + clk_set_rate(clk, CONFIG_PL011_CLOCK); + clk_enable(clk); +} +#endif + +int arch_cpu_init(void) +{ + flush_dcache_all(); + cpu_soc_init(); + clk_init(); + + if (IS_ENABLED(CONFIG_PL011_SERIAL)) + serial_device_init(); + + return 0; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + return 0; +} +#endif + +void reset_cpu(ulong ignored) +{ + void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR; + const u32 sw_rst_enb_bitpos = 3; + const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos; + const u32 sw_rst_bitpos = 12; + const u32 sw_rst_mask = 1 << sw_rst_bitpos; + int pwrcont = 0x224; + int pwrmode = 0x228; + u32 read_value; + + read_value = readl((void *)(clkpwr_reg + pwrcont)); + + read_value &= ~sw_rst_enb_mask; + read_value |= 1 << sw_rst_enb_bitpos; + + writel(read_value, (void *)(clkpwr_reg + pwrcont)); + writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode)); +} + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ -- cgit