From e87c673c206aa3eb75eb94e65d8d50d7fabaf598 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 17 Nov 2016 12:29:56 +0530 Subject: armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain Signed-off-by: Raghav Dogra Signed-off-by: Prabhakar Kushwaha [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index eb03bf44cb..d6ee54642d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -191,7 +191,7 @@ void enable_caches(void) } #endif -static inline u32 initiator_type(u32 cluster, int init_id) +u32 initiator_type(u32 cluster, int init_id) { struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; -- cgit