From 1001502545ff0125c39232cf0e7f26d9213ab55f Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Fri, 3 May 2019 09:41:00 -0400 Subject: CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin Signed-off-by: Trevor Woerner [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/cpu/armv8/fsl-layerscape') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b32f..12d709e23e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -388,7 +388,7 @@ void cpu_name(char *name) strcpy(name, "unknown"); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* * To start MMU before DDR is available, we create MMU table in SRAM. * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three @@ -611,7 +611,7 @@ void enable_caches(void) icache_enable(); dcache_enable(); } -#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ #ifdef CONFIG_TFABOOT enum boot_src __get_boot_src(u32 porsr1) -- cgit