From d171c70716d49f0e14eb357ab645c8e72b791ca1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 5 Nov 2018 18:01:06 +0000 Subject: move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 ++++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index be00bd55ab..e01b029d64 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -33,6 +33,303 @@ DECLARE_GLOBAL_DATA_PTR; +static struct cpu_type cpu_type_list[] = { + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), + CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), + CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), + CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), + CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), + CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), + CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), +}; + +#define EARLY_PGTABLE_SIZE 0x5000 +static struct mm_region early_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, +#ifdef CONFIG_FSL_IFC + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#ifdef CONFIG_FSL_IFC + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif + {}, /* list terminator */ +}; + +static struct mm_region final_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_ARCH_LS2080A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, + CONFIG_SYS_FSL_BOOTROM_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + {}, /* space holder for secure mem */ +#endif + {}, +}; + struct mm_region *mem_map = early_map; void cpu_name(char *name) -- cgit From bb50569dc4c3ac71af075d5e994d0a37579efc51 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 5 Nov 2018 18:01:23 +0000 Subject: armv8: layerscape: Enable routing SError exception In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index ef3987ea84..11b5fb2ec3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1: -- cgit From e3506480466084a09d9882d546c3c3c677b13962 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:01:28 +0000 Subject: armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e01b029d64..336909cfe5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -371,7 +371,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el(); /* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; -- cgit From 535d76a1215064866b1eb7f0aa61796fc32d31c1 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:37 +0000 Subject: armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun Signed-off-by: Rajesh Bhagat --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++++--- 2 files changed, 13 insertions(+), 3 deletions(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fadc0..9092757d1f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB help For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use pins, select it when the pins are assigned to USB. + +config TFABOOT + bool "Support for booting from TFA" + default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via TFA. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 336909cfe5..901ecb943a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -88,7 +88,8 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -139,7 +140,8 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -1236,7 +1238,8 @@ void update_early_mmu_table(void) __weak int dram_init(void) { fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif -- cgit From 4c417384620025a7b64e2bd256e7641529b3ddf8 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:42 +0000 Subject: armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: fix multiple checkpatch issues] Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 189 ++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 901ecb943a..0b6f1e1b47 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -31,6 +31,10 @@ #include #include +#ifdef CONFIG_TFABOOT +#include +#endif + DECLARE_GLOBAL_DATA_PTR; static struct cpu_type cpu_type_list[] = { @@ -581,7 +585,192 @@ void enable_caches(void) icache_enable(); dcache_enable(); } +#endif /* CONFIG_SYS_DCACHE_OFF */ + +#ifdef CONFIG_TFABOOT +enum boot_src __get_boot_src(u32 porsr1) +{ + enum boot_src src = BOOT_SOURCE_RESERVED; + u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; +#if !defined(CONFIG_FSL_LSCH3_2) + u32 val; +#endif + debug("%s: rcw_src 0x%x\n", __func__, rcw_src); + +#if defined(CONFIG_FSL_LSCH3) +#if defined(CONFIG_FSL_LSCH3_2) + switch (rcw_src) { + case RCW_SRC_SDHC1_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_SDHC2_VAL: + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + case RCW_SRC_FLEXSPI_NAND2K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_FLEXSPI_NAND4K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_RESERVED_1_VAL: + src = BOOT_SOURCE_RESERVED; + break; + case RCW_SRC_FLEXSPI_NOR_24B: + src = BOOT_SOURCE_XSPI_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } +#else + val = rcw_src & RCW_SRC_TYPE_MASK; + if (val == RCW_SRC_NOR_VAL) { + val = rcw_src & NOR_TYPE_MASK; + + switch (val) { + case NOR_16B_VAL: + case NOR_32B_VAL: + src = BOOT_SOURCE_IFC_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } else { + /* RCW SRC Serial Flash */ + val = rcw_src & RCW_SRC_SERIAL_MASK; + switch (val) { + case RCW_SRC_QSPI_VAL: + /* RCW SRC Serial NOR (QSPI) */ + src = BOOT_SOURCE_QSPI_NOR; + break; + case RCW_SRC_SD_CARD_VAL: + /* RCW SRC SD Card */ + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_EMMC_VAL: + /* RCW SRC EMMC */ + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + /* RCW SRC I2C1 Extended */ + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } +#endif +#elif defined(CONFIG_FSL_LSCH2) + /* RCW SRC NAND */ + val = rcw_src & RCW_SRC_NAND_MASK; + if (val == RCW_SRC_NAND_VAL) { + val = rcw_src & NAND_RESERVED_MASK; + if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2) + src = BOOT_SOURCE_IFC_NAND; + + } else { + /* RCW SRC NOR */ + val = rcw_src & RCW_SRC_NOR_MASK; + if (val == NOR_8B_VAL || val == NOR_16B_VAL) { + src = BOOT_SOURCE_IFC_NOR; + } else { + switch (rcw_src) { + case QSPI_VAL1: + case QSPI_VAL2: + src = BOOT_SOURCE_QSPI_NOR; + break; + case SD_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } + } #endif + debug("%s: src 0x%x\n", __func__, src); + return src; +} + +enum boot_src get_boot_src(void) +{ + u32 porsr1; + +#if defined(CONFIG_FSL_LSCH3) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + porsr1 = in_be32(&gur->porsr1); +#endif + debug("%s: porsr1 0x%x\n", __func__, porsr1); + + return __get_boot_src(porsr1); +} + +#ifdef CONFIG_ENV_IS_IN_MMC +int mmc_get_env_dev(void) +{ + enum boot_src src = get_boot_src(); + int dev = CONFIG_SYS_MMC_ENV_DEV; + + switch (src) { + case BOOT_SOURCE_SD_MMC: + dev = 0; + break; + case BOOT_SOURCE_SD_MMC2: + dev = 1; + break; + default: + break; + } + + return dev; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_src src = get_boot_src(); + enum env_location env_loc = ENVL_NOWHERE; + + if (prio) + return ENVL_UNKNOWN; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + env_loc = ENVL_FLASH; + break; + case BOOT_SOURCE_QSPI_NOR: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NOR: + env_loc = ENVL_SPI_FLASH; + break; + case BOOT_SOURCE_IFC_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_QSPI_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NAND: + env_loc = ENVL_NAND; + break; + case BOOT_SOURCE_SD_MMC: + /* FALLTHROUGH */ + case BOOT_SOURCE_SD_MMC2: + env_loc = ENVL_MMC; + break; + case BOOT_SOURCE_I2C1_EXTENDED: + /* FALLTHROUGH */ + default: + break; + } + + return env_loc; +} +#endif /* CONFIG_TFABOOT */ u32 initiator_type(u32 cluster, int init_id) { -- cgit From b6c97f4d94144cab494d0844268cca05e04af3d0 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:48 +0000 Subject: armv8: layerscape: remove EL3 specific erratas for TFABOOT Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9092757d1f..1872c66dcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -62,17 +62,17 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 -- cgit From 2141d250f510fb33d6b42ff35bfa8f3fbbc343d0 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:01:52 +0000 Subject: armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg [YS: remove unnecessary braces] Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 77 +++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0b6f1e1b47..e25515ef9b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -33,6 +33,9 @@ #ifdef CONFIG_TFABOOT #include +#ifdef CONFIG_CHAIN_OF_TRUST +#include +#endif #endif DECLARE_GLOBAL_DATA_PTR; @@ -741,6 +744,14 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN; +#ifdef CONFIG_CHAIN_OF_TRUST + /* Check Boot Mode + * If Boot Mode is Secure, return ENVL_NOWHERE + */ + if (fsl_check_boot_mode_secure() == 1) + goto done; +#endif + switch (src) { case BOOT_SOURCE_IFC_NOR: env_loc = ENVL_FLASH; @@ -768,6 +779,9 @@ enum env_location env_get_location(enum env_operation op, int prio) break; } +#ifdef CONFIG_CHAIN_OF_TRUST +done: +#endif return env_loc; } #endif /* CONFIG_TFABOOT */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 54fb0745f9..c0a8e301a5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -24,6 +24,10 @@ #include #endif #include +#ifdef CONFIG_TFABOOT +#include +DECLARE_GLOBAL_DATA_PTR; +#endif bool soc_has_dp_ddr(void) { @@ -679,12 +683,85 @@ int qspi_ahb_init(void) } #endif +#ifdef CONFIG_TFABOOT +#define MAX_BOOTCMD_SIZE 256 + +int fsl_setenv_bootcmd(void) +{ + int ret; + enum boot_src src = get_boot_src(); + char bootcmd_str[MAX_BOOTCMD_SIZE]; + + switch (src) { +#ifdef IFC_NOR_BOOTCOMMAND + case BOOT_SOURCE_IFC_NOR: + sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NOR: + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NOR: + sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef IFC_NAND_BOOTCOMMAND + case BOOT_SOURCE_IFC_NAND: + sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NAND: + sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NAND: + sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef SD_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC: + sprintf(bootcmd_str, SD_BOOTCOMMAND); + break; +#endif +#ifdef SD2_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC2: + sprintf(bootcmd_str, SD2_BOOTCOMMAND); + break; +#endif + default: +#ifdef QSPI_NOR_BOOTCOMMAND + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); +#endif + break; + } + + ret = env_set("bootcmd", bootcmd_str); + if (ret) { + printf("Failed to set bootcmd: ret = %d\n", ret); + return ret; + } + return 0; +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif +#ifdef CONFIG_TFABOOT + /* + * check if gd->env_addr is default_environment; then setenv bootcmd + */ + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) + fsl_setenv_bootcmd(); +#endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); #endif -- cgit From 681d489e6281b9d4a1896ad7b8c926bb2286ed7a Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:58 +0000 Subject: armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e25515ef9b..ca632ebdaa 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1229,12 +1229,96 @@ phys_size_t get_effective_memsize(void) return ea_size; } +#ifdef CONFIG_TFABOOT +phys_size_t tfa_get_dram_size(void) +{ + struct pt_regs regs; + phys_size_t dram_size = 0; + + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = -1; + + smc_call(®s); + if (regs.regs[0]) + return 0; + + dram_size = regs.regs[1]; + return dram_size; +} + +static int tfa_dram_init_banksize(void) +{ + int i = 0, ret = 0; + struct pt_regs regs; + phys_size_t dram_size = tfa_get_dram_size(); + + debug("dram_size %llx\n", dram_size); + + if (!dram_size) + return -EINVAL; + + do { + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = i; + + smc_call(®s); + if (regs.regs[0]) { + ret = -EINVAL; + break; + } + + debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], + regs.regs[2]); + gd->bd->bi_dram[i].start = regs.regs[1]; + gd->bd->bi_dram[i].size = regs.regs[2]; + + dram_size -= gd->bd->bi_dram[i].size; + + i++; + } while (dram_size); + + if (i > 0) + ret = 0; + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + + return ret; +} +#endif + int dram_init_banksize(void) { #ifdef CONFIG_SYS_DP_DDR_BASE_PHY phys_size_t dp_ddr_size; #endif +#ifdef CONFIG_TFABOOT + if (!tfa_dram_init_banksize()) + return 0; +#endif /* * gd->ram_size has the total size of DDR memory, less reserved secure * memory. The DDR extends from low region to high region(s) presuming -- cgit From 5a73ec6169d1db85eacc4ad2fc74dad92a846c9e Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:05 +0000 Subject: armv8: layerscape: skip OCRAM init for TFABOOT OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 11b5fb2ec3..cbc9112eb1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -304,7 +304,8 @@ ENTRY(lowlevel_init) 100: #endif -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_TFABOOT) && \ + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) bl fsl_ocram_init #endif -- cgit From 56db948b85aa7c03c79b2c796500de4523924a9d Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 5 Nov 2018 18:02:09 +0000 Subject: armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ca632ebdaa..36189f7a92 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1) } } #endif + + if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src) + src = BOOT_SOURCE_QSPI_NOR; + debug("%s: src 0x%x\n", __func__, src); return src; } enum boot_src get_boot_src(void) { - u32 porsr1; + struct pt_regs regs; + u32 porsr1 = 0; #if defined(CONFIG_FSL_LSCH3) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - - porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); #elif defined(CONFIG_FSL_LSCH2) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#endif + + if (current_el() == 2) { + regs.regs[0] = SIP_SVC_RCW; - porsr1 = in_be32(&gur->porsr1); + smc_call(®s); + if (!regs.regs[0]) + porsr1 = regs.regs[1]; + } + + if (current_el() == 3 || !porsr1) { +#ifdef CONFIG_FSL_LSCH3 + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + porsr1 = in_be32(&gur->porsr1); #endif + } + debug("%s: porsr1 0x%x\n", __func__, porsr1); return __get_boot_src(porsr1); -- cgit From 339fb297d45fdb98d45c2ea944b40b3e3a63d150 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:13 +0000 Subject: armv8: sec_firmware: change el2_to_aarch32 SMC ID Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 1c0f963e18..af1b2da072 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -68,7 +68,7 @@ ENTRY(armv8_el2_to_aarch32) mov x3, x2 mov x2, x1 mov x1, x4 - ldr x0, =0xc000ff04 + ldr x0, =0xc200ff17 smc #0 ret ENDPROC(armv8_el2_to_aarch32) -- cgit From 2e17cb8a42404201298c53fe752327f59db6ff8e Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:02:19 +0000 Subject: armv8: sec_firmware: return job ring status as true in TFABOOT Returns job ring status as true in TFABOOT, as one job ring is always reserved. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/sec_firmware.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index a13c92e246..8dc0ac9266 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void) */ bool sec_firmware_support_hwrng(void) { +#ifdef CONFIG_TFABOOT + /* return true as TFA has one job ring reserved */ + return true; +#endif if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { return true; } -- cgit From ade32bb47375bdfaf52e151d904e2da5b4eb4344 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:02:31 +0000 Subject: armv8: fsl-layerscape: add support of MC framework for TFA Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 53 ++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c0a8e301a5..0092a22394 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -747,6 +747,54 @@ int fsl_setenv_bootcmd(void) } return 0; } + +int fsl_setenv_mcinitcmd(void) +{ + int ret = 0; + enum boot_src src = get_boot_src(); + + switch (src) { +#ifdef IFC_MC_INIT_CMD + case BOOT_SOURCE_IFC_NAND: + case BOOT_SOURCE_IFC_NOR: + ret = env_set("mcinitcmd", IFC_MC_INIT_CMD); + break; +#endif +#ifdef QSPI_MC_INIT_CMD + case BOOT_SOURCE_QSPI_NAND: + case BOOT_SOURCE_QSPI_NOR: + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); + break; +#endif +#ifdef XSPI_MC_INIT_CMD + case BOOT_SOURCE_XSPI_NAND: + case BOOT_SOURCE_XSPI_NOR: + ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD); + break; +#endif +#ifdef SD_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC: + ret = env_set("mcinitcmd", SD_MC_INIT_CMD); + break; +#endif +#ifdef SD2_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC2: + ret = env_set("mcinitcmd", SD2_MC_INIT_CMD); + break; +#endif + default: +#ifdef QSPI_MC_INIT_CMD + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); +#endif + break; + } + + if (ret) { + printf("Failed to set mcinitcmd: ret = %d\n", ret); + return ret; + } + return 0; +} #endif #ifdef CONFIG_BOARD_LATE_INIT @@ -758,9 +806,12 @@ int board_late_init(void) #ifdef CONFIG_TFABOOT /* * check if gd->env_addr is default_environment; then setenv bootcmd + * and mcinitcmd. */ - if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { fsl_setenv_bootcmd(); + fsl_setenv_mcinitcmd(); + } #endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); -- cgit From 6252faa0da0954b548f05d23c65734cd8c905382 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 27 Sep 2018 10:32:05 +0530 Subject: armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 + .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 71 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1872c66dcd..2d1946ca70 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -348,6 +348,9 @@ config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_2 bool +config SYS_NXP_SRDS_3 + bool + config SYS_HAS_SERDES bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2bef841194..bb50e3d5a7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright 2016-2018 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -16,6 +17,9 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #ifdef CONFIG_SYS_FSL_SRDS_2 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 +static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; +#endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int xfi_dpmac[XFI8 + 1]; @@ -57,6 +61,12 @@ int is_serdes_configured(enum srds_prtcl device) ret |= serdes2_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + + ret |= serdes3_prtcl_map[device]; +#endif return !!ret; } @@ -81,6 +91,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + case NXP_SRDS_3: + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT; + break; #endif default: printf("invalid SerDes%d\n", sd); @@ -200,6 +217,12 @@ struct serdes_prctl_info srds_prctl_info[] = { .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK, .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT }, +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + {.id = 3, + .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT + }, #endif {} /* NULL ENTRY */ }; @@ -340,6 +363,11 @@ int setup_serdes_volt(u32 svdd) struct ccsr_serdes __iomem *serdes2_base = (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + struct ccsr_serdes __iomem *serdes3_base = + (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); + u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); #endif u32 cfg_tmp; int svdd_cur, svdd_tar; @@ -370,6 +398,9 @@ int setup_serdes_volt(u32 svdd) #ifdef CONFIG_SYS_FSL_SRDS_2 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false); +#endif /* Put the all enabled PLL in reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -383,6 +414,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset(cfg_tmp, serdes3_base); +#endif + /* Put the Rx/Tx calibration into reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_rx_tx_cal_reset(serdes1_base); @@ -392,6 +429,10 @@ int setup_serdes_volt(u32 svdd) do_rx_tx_cal_reset(serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_rx_tx_cal_reset(serdes3_base); +#endif + ret = set_serdes_volt(svdd); if (ret < 0) { printf("could not change SVDD\n"); @@ -408,6 +449,11 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_serdes_enable(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_serdes_enable(cfg_tmp, serdes3_base); +#endif /* Wait for at at least 625us, ensure the PLLs being reset are locked */ udelay(800); @@ -422,6 +468,13 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_pll_lock(cfg_tmp, serdes2_base); #endif + +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_lock(cfg_tmp, serdes3_base); +#endif + /* Take the all enabled lanes out of reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); @@ -430,6 +483,10 @@ int setup_serdes_volt(u32 svdd) do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true); +#endif + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; @@ -441,6 +498,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset_done(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset_done(cfg_tmp, serdes3_base); +#endif + return ret; } @@ -472,4 +535,12 @@ void fsl_serdes_init(void) FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + serdes_init(NXP_SRDS_3, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, + FSL_CHASSIS3_SRDS3_REGSR, + FSL_CHASSIS3_SRDS3_PRTCL_MASK, + FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, + serdes3_prtcl_map); +#endif } -- cgit From d6fdec211f7913c97917ba262fa257fdcb6b000e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 29 Oct 2018 09:11:29 +0000 Subject: armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 +++++++++++++-- .../cpu/armv8/fsl-layerscape/doc/README.lsch3_2 | 27 ++++++++++++++++++++++ 3 files changed, 46 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2d1946ca70..650ac94165 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -180,6 +180,9 @@ config FSL_LSCH2 config FSL_LSCH3 bool +config NXP_LSCH3_2 + bool + config FSL_MC_ENET bool "Management Complex network" depends on ARCH_LS2080A || ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 36189f7a92..5c62bcc2e9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -120,6 +120,13 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, @@ -266,6 +273,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, @@ -595,13 +609,13 @@ enum boot_src __get_boot_src(u32 porsr1) { enum boot_src src = BOOT_SOURCE_RESERVED; u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; -#if !defined(CONFIG_FSL_LSCH3_2) +#if !defined(CONFIG_NXP_LSCH3_2) u32 val; #endif debug("%s: rcw_src 0x%x\n", __func__, rcw_src); #if defined(CONFIG_FSL_LSCH3) -#if defined(CONFIG_FSL_LSCH3_2) +#if defined(CONFIG_NXP_LSCH3_2) switch (rcw_src) { case RCW_SRC_SDHC1_VAL: src = BOOT_SOURCE_SD_MMC; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 new file mode 100644 index 0000000000..6d4bd0b80a --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 @@ -0,0 +1,27 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +NXP LayerScape with Chassis Generation 3.2 + +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 +for example LX2160A. + +This architecture is enhancement over Chassis Generation 3 with +few differences mentioned below + +1)DDR Layout +============ +Entire DDR region splits into three regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, + - Region 3 is at address 0x60_0000_0000 to the top of memory, + for example 140GB, 0x63_7fff_ffff. + +All DDR memory is marked as cache-enabled. + +2)IFC is removed + +3)Number of I2C controllers increased to 8 -- cgit From 4909b89ec763f0c7030fa8474f9b6c5df866b01f Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 29 Oct 2018 09:17:09 +0000 Subject: armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei Signed-off-by: Hou Zhiqiang Signed-off-by: Meenakshi Aggarwal Signed-off-by: Vabhav Sharma Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 52 +++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 57 +++++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 36 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +++++++++++++++++++++ 7 files changed, 293 insertions(+), 7 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 650ac94165..2b086da79b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -170,6 +170,42 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -185,7 +221,7 @@ config NXP_LSCH3_2 config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -202,6 +238,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -300,6 +337,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -342,6 +380,9 @@ config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCN504 bool +config SYS_FSL_HAS_CCN508 + bool + config SYS_FSL_HAS_DP_DDR bool @@ -404,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -464,13 +506,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -506,7 +550,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 91fdbad8be..e9bc987a9c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2016-2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 5c62bcc2e9..1fc025b581 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -60,6 +60,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -246,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -366,6 +369,10 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); +#ifdef CONFIG_ARCH_LX2160A + if (IS_C_PROCESSOR(svr)) + strcat(name, "C"); +#endif if (IS_E_PROCESSOR(svr)) strcat(name, "E"); @@ -1164,10 +1171,16 @@ void __efi_runtime reset_cpu(ulong addr) { u32 val; +#ifdef CONFIG_ARCH_LX2160A + val = in_le32(rstcr); + val |= 0x01; + out_le32(rstcr, val); +#else /* Raise RESET_REQ_B */ val = scfg_in32(rstcr); val |= 0x02; scfg_out32(rstcr, val); +#endif } #ifdef CONFIG_EFI_LOADER diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab9052d..a0e262169e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index bb50e3d5a7..ab1be3fa54 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -166,6 +201,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, (int)lane_prtcl); break; } +#endif #endif } } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index cbc9112eb1..6721a579ea 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -354,7 +354,7 @@ get_svr: ret #endif -#ifdef CONFIG_SYS_FSL_HAS_CCN504 +#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000000..a04a370268 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} -- cgit