From e3506480466084a09d9882d546c3c3c677b13962 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:01:28 +0000 Subject: armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e01b029d64..336909cfe5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -371,7 +371,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el(); /* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; -- cgit