From ddcf13b15231ee2dca99285349b143c365ce5173 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sun, 5 Aug 2012 09:05:30 +0000 Subject: mxs: prefix register acessor macros with 'mxs' prefix As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador --- arch/arm/cpu/arm926ejs/mxs/clock.c | 4 ++-- arch/arm/cpu/arm926ejs/mxs/iomux.c | 6 +++--- arch/arm/cpu/arm926ejs/mxs/mx28.c | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 0439f9c0ea..3e29c56e8b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -207,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) return; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); + (ssp * sizeof(struct mxs_register_32)); clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) @@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) return XTAL_FREQ_KHZ; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); + (ssp * sizeof(struct mxs_register_32)); tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 12916b6d60..73f1446907 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) { u32 reg, ofs, bp, bm; void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mx28_register_32 *mxs_reg; + struct mxs_register_32 *mxs_reg; /* muxsel */ ofs = 0x100; @@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) /* vol */ if (PAD_VOL_VALID(pad)) { bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); if (PAD_VOL(pad)) writel(1 << bp, &mxs_reg->reg_set); else @@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs = PULL_OFFSET; ofs += PAD_BANK(pad) * 0x10; bp = PAD_PIN(pad); - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); if (PAD_PULL(pad)) writel(1 << bp, &mxs_reg->reg_set); else diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28.c b/arch/arm/cpu/arm926ejs/mxs/mx28.c index cf7a50f9d1..65fcd75bd8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mx28.c +++ b/arch/arm/cpu/arm926ejs/mxs/mx28.c @@ -81,7 +81,7 @@ void enable_caches(void) #endif } -int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) +int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == mask) @@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) +int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == 0) @@ -103,7 +103,7 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_reset_block(struct mx28_register_32 *reg) +int mx28_reset_block(struct mxs_register_32 *reg) { /* Clear SFTRST */ writel(MX28_BLOCK_SFTRST, ®->reg_clr); -- cgit