From 4a87fea6de30b6e9c59a5abb6da1d0d84c984d15 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 25 May 2020 12:19:48 +0200 Subject: ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL This patch allows to switch the CPU frequency to 800MHz on the ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM using the STM32MP15x SOC and when it is supported by the HW (for STM32MP15xD and STM32MP15xF). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi') diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index b16dc28d47..ef3e7f45a3 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -129,15 +129,6 @@ CLK_LPTIM45_LSE >; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - cfg = < 2 80 0 0 0 PQR(1,0,0) >; - frac = < 0x800 >; - u-boot,dm-pre-reloc; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; -- cgit