From 92226b5a6d00689dce5c1406913ca97b0b89bda9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 Jul 2018 11:34:00 +0200 Subject: arm: zynqmp: Fix sdhci clock in emmc1 mini configuration Add missing clocks property with fix clock-names property to be aligned with emmc0 configuration and binding doc. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-mini-emmc1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index d1549b6dc6..530ab3cdc2 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -52,7 +52,8 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_xin"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk_xin &clk_xin>; xlnx,device_id = <1>; }; }; -- cgit From 7996fcca9d401437527d9e9a464cb79965c90c98 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 Jul 2018 10:16:21 +0200 Subject: arm: zynq: Remove fclk-enable property for cse-nor target Mini cse NOR configuration is running without PL that's why there is no reason to enable clock to PL. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-nor.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index ba6f9a1a79..edc8f59f6c 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -56,7 +56,6 @@ clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", -- cgit From df0996907018cef836e17a076422fd22daa435e0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 Jul 2018 10:17:17 +0200 Subject: arm: zynq: Fix indentation for zynq-cse targets Trivial DT style fixes. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-nand.dts | 3 +-- arch/arm/dts/zynq-cse-nor.dts | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 9b1dd19a85..1e16d7fab9 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -38,7 +38,7 @@ #size-cells = <1>; ranges; - slcr: slcr@f8000000 { + slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; @@ -72,7 +72,6 @@ }; }; }; - }; &dcc { diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index edc8f59f6c..9710abadcf 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -79,7 +79,6 @@ }; }; }; - }; &dcc { -- cgit From 58f449676ac29938ea2970e240a2defe99240a8e Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Tue, 24 Jul 2018 11:31:19 -0400 Subject: arm: zynq: add support for the zybo z7 board The board is manufactured by Digilent Main features: - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20) - RAM: 1 GB DDR3L - FLASH: 16 MB QSPI - 1 Gbps Ethernet - USB 2.0 - microSD slot - Pcam camera connector - HDMI Tx and Rx - Audio codec: stereo out, stereo in, mic - 5 (Z7-10) or 6 (Z7-20) Pmod ports - 6 push-buttons, 4 switches, 5 LEDs - 1 (Z7-10) or 2 (Z7-20) RGB LEDs Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/zynq-zybo-z7.dts | 81 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynq-zybo-z7.dts (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 89032bb545..797e5756a3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -149,7 +149,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ zynq-zturn.dtb \ - zynq-zybo.dtb + zynq-zybo.dtb \ + zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts new file mode 100644 index 0000000000..3f8a3bfa0f --- /dev/null +++ b/arch/arm/dts/zynq-zybo-z7.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. + */ +/dts-v1/; +#include "zynq-7000.dtsi" +#include + +/ { + model = "Digilent Zybo Z7 board"; + compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + ld4 { + label = "zynq-zybo-z7:green:ld4"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_phy0: phy0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; -- cgit From 2570e12960486cdf2b1e0e3fb8f6100116ccf65e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Jul 2018 16:27:00 +0200 Subject: arm64: zynqmp: Add support for Avnet Ultra96 Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files and point to origin internal board name. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/avnet-ultra96-rev1.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm/dts/avnet-ultra96-rev1.dts (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 797e5756a3..ebfa227262 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -152,6 +152,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ + avnet-ultra96-rev1.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts new file mode 100644 index 0000000000..88aa06fa78 --- /dev/null +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Avnet Ultra96 rev1 + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp-zcu100-revC.dts" + +/ { + model = "Avnet Ultra96 Rev1"; + compatible = "avnet,ultra96-rev1", "avnet,ultra96", + "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", + "xlnx,zynqmp"; +}; -- cgit From a492fdffa3c86f6b8420b6433a2ce07271597324 Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Fri, 27 Jul 2018 04:43:42 -0400 Subject: arm: zynq: dts: add spi flash node to zedboard Add a flash node to fix the detection of the memory IC. With the changes introduced with commit 8fee8845e754 ("enf_sf: reuse setup_flash_device instead of open coding it") the SPI speed is now read from device-tree or a default value is applied. This replaced the old behavior of setting the SPI speed to CONFIG_ENV_SPI_MAX_HZ. As this board didn't have a flash node, the default value was applied to the SPI speed, producing an error when probing the flash memory (speed too slow). Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zed.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 24eccf1633..9c505fb7b8 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -51,6 +51,13 @@ &qspi { u-boot,dm-pre-reloc; status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "spansion,s25fl256s", "spi-flash"; + reg = <0>; + spi-max-frequency = <30000000>; + m25p,fast-read; + }; }; &sdhci0 { -- cgit