From 420d44678119a5df1fcc154d1c33d35fd9722285 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 21 May 2019 12:07:23 +0200 Subject: arm64: zynqmp: Rename zc1275 to zcu1275 Name of this platform has changed and released to customers that's why name has also changed. Signed-off-by: Michal Simek Series-to: uboot --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/zynqmp-zc1275-revA.dts | 72 -------------------------------- arch/arm/dts/zynqmp-zc1275-revB.dts | 79 ----------------------------------- arch/arm/dts/zynqmp-zcu1275-revA.dts | 73 ++++++++++++++++++++++++++++++++ arch/arm/dts/zynqmp-zcu1275-revB.dts | 80 ++++++++++++++++++++++++++++++++++++ 5 files changed, 155 insertions(+), 153 deletions(-) delete mode 100644 arch/arm/dts/zynqmp-zc1275-revA.dts delete mode 100644 arch/arm/dts/zynqmp-zc1275-revB.dts create mode 100644 arch/arm/dts/zynqmp-zcu1275-revA.dts create mode 100644 arch/arm/dts/zynqmp-zcu1275-revB.dts (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b437f7500c..ff181978de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -253,10 +253,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu104-revC.dtb \ zynqmp-zcu106-revA.dtb \ zynqmp-zcu111-revA.dtb \ + zynqmp-zcu1275-revA.dtb \ + zynqmp-zcu1275-revB.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ - zynqmp-zc1275-revA.dtb \ - zynqmp-zc1275-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm017-dc3.dtb \ diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts deleted file mode 100644 index 82c30a3fbe..0000000000 --- a/arch/arm/dts/zynqmp-zc1275-revA.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1275 - * - * (C) Copyright 2017 - 2018, Xilinx, Inc. - * - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - spi0 = &qspi; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&qspi { - status = "okay"; - flash@0 { - compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ - spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@qspi-linux { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@qspi-device-tree { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@qspi-rootfs { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5E0000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts deleted file mode 100644 index 0473503afa..0000000000 --- a/arch/arm/dts/zynqmp-zc1275-revB.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Xilinx ZynqMP ZC1275 RevB - * - * (C) Copyright 2018, Xilinx, Inc. - * - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1275 RevB"; - compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - spi0 = &qspi; - mmc0 = &sdhci1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&qspi { - status = "okay"; - flash@0 { - compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@qspi-linux { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@qspi-device-tree { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@qspi-rootfs { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5E0000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - no-1-8-v; - xlnx,mio_bank = <1>; -}; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts new file mode 100644 index 0000000000..c22de576a5 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU1275 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZCU1275 RevA"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", + "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts new file mode 100644 index 0000000000..34c4becd43 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU1275 RevB + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZCU1275 RevB"; + compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", + "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + mmc0 = &sdhci1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; +}; -- cgit From ac80ac09c84fda3b5ae2df865ee9f2acf37a91db Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Tue, 11 Jun 2019 18:39:41 +0200 Subject: arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the only publicly-available compatible carrier card. The SoM is based on the EV version of the Xilinx ZynqMP SoC+FPGA. The psu_init_gpl.c file has been generated from the board definition files at [0] using Vivado 2018.3 and then minimized by tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since it is not mentioned in device tree and fixed a checkpatch error. [0] https://github.com/Avnet/bdf/tree/3686c9ff7d2f0467fb4fcf39f861b8d6ff183b12/ultrazed_7ev_cc/1.1 Signed-off-by: Luca Ceresoli Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + ...vnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 59 ++++++++++++++++++++++ arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi | 56 ++++++++++++++++++++ 3 files changed, 116 insertions(+) create mode 100644 arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts create mode 100644 arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ff181978de..aa94c49f37 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -240,6 +240,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ + avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts new file mode 100644 index 0000000000..ac641ff1a5 --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/* + * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM) + * http://ultrazed.org/product/ultrazed-ev-carrier-card + */ + +/dts-v1/; + +#include "avnet-ultrazedev-som-v1.0.dtsi" + +/ { + model = "Avnet UltraZed EV Carrier Card v1.0"; + compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0", + "xlnx,zynqmp"; + chosen { + stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; + }; + aliases { + ethernet0 = &gem3; + serial0 = &uart0; + }; +}; + +&uart0 { + device_type = "serial"; + status = "okay"; +}; + +&i2c_cc { + /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */ + eeprom: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* IDT Versa Clock 5P49V5935B */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5935"; + reg = <0x6a>; + #clock-cells = <1>; + }; +}; + +/* Ethernet RJ-45 */ +&gem3 { + status = "okay"; +}; + +/* microSD card slot */ +&sdhci1 { + status = "okay"; + xlnx,mio_bank = <1>; + clock-frequency = <199998000>; + max-frequency = <50000000>; + no-1-8-v; + disable-wp; +}; diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi new file mode 100644 index 0000000000..b635db649f --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/* + * UltraZed-EV SoM v1 + * http://ultrazed.org/product/ultrazed-ev + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "Avnet UltraZed EV SoM v1.0"; + compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp"; + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */ + <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + /* I2C connected to Carrier Card via JX3A1/JX3C1 */ + i2c_cc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */ +&gem3 { + phy-mode = "rgmii-id"; + phy-handle = <&gem3phy>; + gem3phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */ +&sdhci0 { + status = "okay"; + xlnx,mio_bank = <0>; + clock-frequency = <199998000>; +}; -- cgit