From c93adc08f393bc401c5929e1045d72dfbea3e126 Mon Sep 17 00:00:00 2001 From: "maxims@google.com" Date: Mon, 17 Apr 2017 12:00:25 -0700 Subject: aspeed: Device Tree configuration for Reset Driver Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko Reviewed-by: Simon Glass --- arch/arm/dts/ast2500-evb.dts | 15 +++++++++++++++ arch/arm/dts/ast2500-u-boot.dtsi | 10 ++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index dc13952fb8..723941ac0b 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -21,3 +21,18 @@ &sdrammc { clock-frequency = <400000000>; }; + +&wdt1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&wdt2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&wdt3 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index c95a7ba835..faeeec1be4 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,4 +1,5 @@ #include +#include #include "ast2500.dtsi" @@ -11,12 +12,21 @@ #reset-cells = <1>; }; + rst: reset-controller { + u-boot,dm-pre-reloc; + compatible = "aspeed,ast2500-reset"; + aspeed,wdt = <&wdt1>; + #reset-cells = <1>; + }; + sdrammc: sdrammc@1e6e0000 { u-boot,dm-pre-reloc; compatible = "aspeed,ast2500-sdrammc"; reg = <0x1e6e0000 0x174 0x1e6e0200 0x1d4 >; + #reset-cells = <1>; clocks = <&scu PLL_MPLL>; + resets = <&rst AST_RESET_SDRAM>; }; ahb { -- cgit