From 50a082a88c54975eaa6b6ae39b50936802783387 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:15 -0500 Subject: arm: imx: imx-common: init: move arch init common setup Move common imx6 arch init setup, init.c can be extended and reused to support imx7 SoC keeping init arch common code. Signed-off-by: Adrian Alonso --- arch/arm/imx-common/init.c | 100 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 arch/arm/imx-common/init.c (limited to 'arch/arm/imx-common/init.c') diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c new file mode 100644 index 0000000000..f7ed038d8e --- /dev/null +++ b/arch/arm/imx-common/init.c @@ -0,0 +1,100 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +void init_aips(void) +{ + struct aipstz_regs *aips1, *aips2; +#ifdef CONFIG_MX6SX + struct aipstz_regs *aips3; +#endif + + aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; + aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; +#ifdef CONFIG_MX6SX + aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; +#endif + + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips1->mprot0); + writel(0x77777777, &aips1->mprot1); + writel(0x77777777, &aips2->mprot0); + writel(0x77777777, &aips2->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips1->opacr0); + writel(0x00000000, &aips1->opacr1); + writel(0x00000000, &aips1->opacr2); + writel(0x00000000, &aips1->opacr3); + writel(0x00000000, &aips1->opacr4); + writel(0x00000000, &aips2->opacr0); + writel(0x00000000, &aips2->opacr1); + writel(0x00000000, &aips2->opacr2); + writel(0x00000000, &aips2->opacr3); + writel(0x00000000, &aips2->opacr4); + +#ifdef CONFIG_MX6SX + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); +#endif +} + +#define SRC_SCR_WARM_RESET_ENABLE 0 + +void init_src(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + + /* + * force warm reset sources to generate cold reset + * for a more reliable restart + */ + val = readl(&src_regs->scr); + val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE); + writel(val, &src_regs->scr); +} + +void boot_mode_apply(unsigned cfg_val) +{ + unsigned reg; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + writel(cfg_val, &psrc->gpr9); + reg = readl(&psrc->gpr10); + if (cfg_val) + reg |= 1 << 28; + else + reg &= ~(1 << 28); + writel(reg, &psrc->gpr10); +} -- cgit From 75a565f2977b423c43a9ebbc6858d708b36b1194 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:20 -0500 Subject: arm: imx-common: init: extend init_aips to support imx7 Extend init_aips to support imx7 SoC, use is_soc_type and is_cpu_type to resolve at run time aips3 settings Signed-off-by: Adrian Alonso --- arch/arm/imx-common/init.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-) (limited to 'arch/arm/imx-common/init.c') diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index f7ed038d8e..f1d43142a2 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -13,16 +13,11 @@ void init_aips(void) { - struct aipstz_regs *aips1, *aips2; -#ifdef CONFIG_MX6SX - struct aipstz_regs *aips3; -#endif + struct aipstz_regs *aips1, *aips2, *aips3; aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; -#ifdef CONFIG_MX6SX aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; -#endif /* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -49,25 +44,26 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); -#ifdef CONFIG_MX6SX - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, &aips3->mprot0); - writel(0x77777777, &aips3->mprot1); + if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) + { + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1); - /* - * Set all OPACRx to be non-bufferable, not require - * supervisor privilege level for access,allow for - * write access and untrusted master access. - */ - writel(0x00000000, &aips3->opacr0); - writel(0x00000000, &aips3->opacr1); - writel(0x00000000, &aips3->opacr2); - writel(0x00000000, &aips3->opacr3); - writel(0x00000000, &aips3->opacr4); -#endif + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); + } } #define SRC_SCR_WARM_RESET_ENABLE 0 -- cgit From 648539c906bb3b039b503b9b6325076eff4d9e5d Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:21 -0500 Subject: arm: imx-common: init: rework wdog settings for imx6/imx7 Rework imx_set_wdog_powerdown to be reused by imx6 and imx7 Signed-off-by: Adrian Alonso --- arch/arm/imx-common/init.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/imx-common/init.c') diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index f1d43142a2..56d5010449 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -66,6 +66,27 @@ void init_aips(void) } } +void imx_set_wdog_powerdown(bool enable) +{ + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; +#ifdef CONFIG_MX7D + struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR; +#endif + + /* Write to the PDE (Power Down Enable) bit */ + writew(enable, &wdog1->wmcr); + writew(enable, &wdog2->wmcr); + + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || + is_soc_type(MXC_SOC_MX7)) + writew(enable, &wdog3->wmcr); +#ifdef CONFIG_MX7D + writew(enable, &wdog4->wmcr); +#endif +} + #define SRC_SCR_WARM_RESET_ENABLE 0 void init_src(void) -- cgit From 4406da0f49dd6aa96c297884911094ff903a8f77 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 15 Sep 2015 14:05:06 +0800 Subject: imx-common: wrap boot_mode_apply with CONFIG_CMD_BMODE boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/imx-common/init.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/imx-common/init.c') diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 56d5010449..058cf79744 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -103,6 +103,7 @@ void init_src(void) writel(val, &src_regs->scr); } +#ifdef CONFIG_CMD_BMODE void boot_mode_apply(unsigned cfg_val) { unsigned reg; @@ -115,3 +116,4 @@ void boot_mode_apply(unsigned cfg_val) reg &= ~(1 << 28); writel(reg, &psrc->gpr10); } +#endif -- cgit From f697c2acca9ff02c9b0cf480a4a726ed9626a53a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 15 Sep 2015 14:05:08 +0800 Subject: imx: fix coding style Fix coding style. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/imx-common/init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/imx-common/init.c') diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 058cf79744..15dab1d904 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -44,8 +44,7 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); - if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) - { + if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) { /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. -- cgit