From 552a848e4f75e224515269a84a1155c84b762bc7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 29 Jun 2017 10:16:06 +0200 Subject: imx: reorganize IMX code as other SOCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic CC: Fabio Estevam CC: Akshay Bhat CC: Ken Lin CC: Marek Vasut CC: Heiko Schocher CC: "Sébastien Szymanski" CC: Christian Gmeiner CC: Stefan Roese CC: Patrick Bruenn CC: Troy Kisky CC: Nikita Kiryanov CC: Otavio Salvador CC: "Eric Bénard" CC: Jagan Teki CC: Ye Li CC: Peng Fan CC: Adrian Alonso CC: Alison Wang CC: Tim Harvey CC: Martin Donnelly CC: Marcin Niestroj CC: Lukasz Majewski CC: Adam Ford CC: "Albert ARIBAUD (3ADEV)" CC: Boris Brezillon CC: Soeren Moch CC: Richard Hu CC: Wig Cheng CC: Vanessa Maegima CC: Max Krummenacher CC: Stefan Agner CC: Markus Niebel CC: Breno Lima CC: Francesco Montefoschi CC: Jaehoon Chung CC: Scott Wood CC: Joe Hershberger CC: Anatolij Gustschin CC: Simon Glass CC: "Andrew F. Davis" CC: "Łukasz Majewski" CC: Patrice Chotard CC: Nobuhiro Iwamatsu CC: Hans de Goede CC: Masahiro Yamada CC: Stephen Warren CC: Andre Przywara CC: "Álvaro Fernández Rojas" CC: York Sun CC: Xiaoliang Yang CC: Chen-Yu Tsai CC: George McCollister CC: Sven Ebenfeld CC: Filip Brozovic CC: Petr Kulhavy CC: Eric Nelson CC: Bai Ping CC: Anson Huang CC: Sanchayan Maity CC: Lokesh Vutla CC: Patrick Delaunay CC: Gary Bisson CC: Alexander Graf CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam Reviewed-by: Christian Gmeiner --- arch/arm/imx-common/timer.c | 139 -------------------------------------------- 1 file changed, 139 deletions(-) delete mode 100644 arch/arm/imx-common/timer.c (limited to 'arch/arm/imx-common/timer.c') diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c deleted file mode 100644 index 9b011147d6..0000000000 --- a/arch/arm/imx-common/timer.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -/* General purpose timers registers */ -struct mxc_gpt { - unsigned int control; - unsigned int prescaler; - unsigned int status; - unsigned int nouse[6]; - unsigned int counter; -}; - -static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */ -#define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ -#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ -#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ -#define GPTCR_CLKSOURCE_MASK (0x7 << 6) -#define GPTCR_TEN 1 /* Timer enable */ - -#define GPTPR_PRESCALER24M_SHIFT 12 -#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT) - -DECLARE_GLOBAL_DATA_PTR; - -static inline int gpt_has_clk_source_osc(void) -{ -#if defined(CONFIG_MX6) - if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || - is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || - is_mx6ull() || is_mx6sll()) - return 1; - - return 0; -#else - return 0; -#endif -} - -static inline ulong gpt_get_clk(void) -{ -#ifdef CONFIG_MXC_GPT_HCLK - if (gpt_has_clk_source_osc()) - return MXC_HCLK >> 3; - else - return mxc_get_clock(MXC_IPG_PERCLK); -#else - return MXC_CLK32; -#endif -} - -int timer_init(void) -{ - int i; - - /* setup GP Timer 1 */ - __raw_writel(GPTCR_SWR, &cur_gpt->control); - - /* We have no udelay by now */ - for (i = 0; i < 100; i++) - __raw_writel(0, &cur_gpt->control); - - i = __raw_readl(&cur_gpt->control); - i &= ~GPTCR_CLKSOURCE_MASK; - -#ifdef CONFIG_MXC_GPT_HCLK - if (gpt_has_clk_source_osc()) { - i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; - - /* - * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC - * Enable bit and prescaler - */ - if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() || - is_mx6sll()) { - i |= GPTCR_24MEN; - - /* Produce 3Mhz clock */ - __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), - &cur_gpt->prescaler); - } - } else { - i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN; - } -#else - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; -#endif - __raw_writel(i, &cur_gpt->control); - - return 0; -} - -unsigned long timer_read_counter(void) -{ - return __raw_readl(&cur_gpt->counter); /* current tick value */ -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gpt_get_clk(); -} - -/* - * This function is intended for SHORT delays only. - * It will overflow at around 10 seconds @ 400MHz, - * or 20 seconds @ 200MHz. - */ -unsigned long usec2ticks(unsigned long _usec) -{ - unsigned long long usec = _usec; - - usec *= get_tbclk(); - usec += 999999; - do_div(usec, 1000000); - - return usec; -} -- cgit