From 6d9b82d085ea810c7bb2ed5203522e45cc72c336 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Thu, 31 Aug 2017 16:12:53 +0530 Subject: armv8: ls1088a: Add NXP LS1088A SoC support LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang Signed-off-by: Prabhakar Kushwaha Signed-off-by: Ashish Kumar Signed-off-by: Raghav Dogra Signed-off-by: Shaohui Xie [YS: Revised commit message] Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape/cpu.h') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 3d564d6610..a0dac86bab 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -24,6 +24,10 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), + CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), + CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), + CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), }; #ifndef CONFIG_SYS_DCACHE_OFF -- cgit