From 4de6ce1594fcff6fa9e626d094fa922f4889e167 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Mon, 8 Aug 2016 15:07:20 +0800 Subject: armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian [York Sun: Reformatted commit message] Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index df5187195d..3d00909b2c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -335,6 +335,8 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 +#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 +#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 /* Supplemental Configuration Unit */ struct ccsr_scfg { -- cgit