From c4dc68b02ff9f6c1ccb088a06cf0445e4031f093 Mon Sep 17 00:00:00 2001 From: Calvin Johnson Date: Thu, 8 Mar 2018 15:30:33 +0530 Subject: armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson Signed-off-by: Anjaneyulu Jagarlmudi Acked-by: Joe Hershberger --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d6f0c5bf3a..af68af471e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -205,6 +205,8 @@ struct sys_info { /* Device Configuration and Pin Control */ #define DCFG_DCSR_PORCR1 0x0 +#define DCFG_DCSR_ECCCR2 0x524 +#define DISABLE_PFE_ECC BIT(13) struct ccsr_gur { u32 porsr1; /* POR status 1 */ @@ -410,6 +412,14 @@ struct ccsr_gur { #define SCFG_PFEASBCR_ARSNP BIT(27) #define SCFG_PFEASBCR_AWSNP BIT(26) +/* WR_QoS1 PFE bit definitions */ +#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) +#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) + +/* RD_QoS1 PFE bit definitions */ +#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) +#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) + /* Supplemental Configuration Unit */ struct ccsr_scfg { u8 res_000[0x100-0x000]; -- cgit