From b7f2bbfff6dcc2d5989bb1d20500c431f7927daf Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:31 +0530 Subject: armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson Signed-off-by: Makarand Pawagi Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape/ns_access.h') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index a3ccdb03c7..db76066c80 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -69,7 +69,12 @@ enum csu_cslx_ind { CSU_CSLX_IIC4 = 77, CSU_CSLX_WDT4, CSU_CSLX_WDT3, + CSU_CSLX_ESDHC2 = 80, CSU_CSLX_WDT5 = 81, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, CSU_CSLX_FTM2 = 86, CSU_CSLX_FTM1, CSU_CSLX_FTM4, @@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = { {CSU_CSLX_IIC4, CSU_ALL_RW}, {CSU_CSLX_WDT4, CSU_ALL_RW}, {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_ESDHC2, CSU_ALL_RW}, {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_SAI2, CSU_ALL_RW}, + {CSU_CSLX_SAI1, CSU_ALL_RW}, + {CSU_CSLX_SAI4, CSU_ALL_RW}, + {CSU_CSLX_SAI3, CSU_ALL_RW}, {CSU_CSLX_FTM2, CSU_ALL_RW}, {CSU_CSLX_FTM1, CSU_ALL_RW}, {CSU_CSLX_FTM4, CSU_ALL_RW}, -- cgit