From a78df40cbabe2cb96e0d2fc18a64759302f9e809 Mon Sep 17 00:00:00 2001 From: Nipun Gupta Date: Mon, 20 Aug 2018 16:01:14 +0530 Subject: u-boot: fixup the iommu-map property of fsl-mc node The iommu-map property in the fsl-mc node is updated by valid stream-ids by u-boot. This patch is to fixup this property for LS208x and LS1088. Signed-off-by: Nipun Gupta Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index afea9b8da8..8d002da3ed 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -35,6 +35,9 @@ * -DPAA2 * -u-boot will allocate a range of stream IDs to be used by the Management * Complex for containers and will set these values in the MC DPC image. + * -u-boot will fixup the iommu-map property in the fsl-mc node in the + * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt + * for more info on the msi-map definition) * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * -- cgit From 6fae6a1fd6bf5001a372701e0764ab0820760d55 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Mon, 27 Aug 2018 17:33:57 +0300 Subject: armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor [York S: revised commit message] Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index be0a6ae363..8c10526a6c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -85,6 +85,8 @@ #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) +#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) -- cgit From 21310793566471758afb24ffb2ad9590f5773670 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Mon, 27 Aug 2018 17:33:58 +0300 Subject: armv8: ls1043a: advertise QMan v3 in configuration The QMan IP block in this SoC is version 3.2 so advertise this in the SoC configuration header. Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8a05148136..bd4ca88e16 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -195,6 +195,7 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -- cgit From dc29a4c1773f7cebacb91dd076bc4293eb065d48 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Mon, 27 Aug 2018 17:33:59 +0300 Subject: armv8: ls1043a: add icid setup support Reuse the existing ICID setup code done for LS1046A smmu enablement and add the equivalent setup for LS1043A chips. Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a70c866651..a3f473fe28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -68,6 +68,10 @@ void fdt_fixup_icid(void *blob); #define SET_DEBUG_ICID(streamid) \ SET_SCFG_ICID(NULL, streamid, debug_icid, 0) +#define SET_QE_ICID(streamid) \ + SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\ + QE_BASE_ADDR) + #define SET_QMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ offsetof(struct ccsr_qman, liodnr) + \ -- cgit