From c8381bf435ddb104594df00411a8ebd049dd753c Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Tue, 31 Mar 2015 11:40:44 +0200 Subject: lpc32xx: mtd: nand: add MLC NAND controller The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) --- arch/arm/include/asm/arch-lpc32xx/clk.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-lpc32xx/clk.h') diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 92f6c15f20..bc7d33da01 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -147,6 +147,10 @@ struct clk_pm_regs { /* DMA Clock Control Register bits */ #define CLK_DMA_ENABLE (1 << 0) +/* NAND Clock Control Register bits */ +#define CLK_NAND_MLC (1 << 1) +#define CLK_NAND_MLC_INT (1 << 5) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); -- cgit From 5e862b95399e6e5ea7748ee29a38756685d622fd Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Tue, 31 Mar 2015 11:40:45 +0200 Subject: lpc32xx: i2c: add LPC32xx I2C interface support Signed-off-by: Albert ARIBAUD (3ADEV) --- arch/arm/include/asm/arch-lpc32xx/clk.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-lpc32xx/clk.h') diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index bc7d33da01..781ac07103 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -123,6 +123,10 @@ struct clk_pm_regs { #define CLK_MAC_SLAVE (1 << 1) #define CLK_MAC_REG (1 << 0) +/* I2C Clock Control Register bits */ +#define CLK_I2C2_ENABLE (1 << 1) +#define CLK_I2C1_ENABLE (1 << 0) + /* Timer Clock Control1 Register bits */ #define CLK_TIMCLK_MOTOR (1 << 6) #define CLK_TIMCLK_TIMER3 (1 << 5) -- cgit From 981219eebe3cc29f155a37951788c18786260514 Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Tue, 31 Mar 2015 11:40:47 +0200 Subject: lpc32xx: add LPC32xx SSP support (SPI mode) Reviewed-by: Jagannadha Sutradharudu Teki Signed-off-by: Albert ARIBAUD (3ADEV) --- arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/arch-lpc32xx/clk.h') diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 781ac07103..2cb5703877 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -155,6 +155,9 @@ struct clk_pm_regs { #define CLK_NAND_MLC (1 << 1) #define CLK_NAND_MLC_INT (1 << 5) +/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); -- cgit From 412ae53aadb53cd63e754d638bafe6e426aeafee Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\(3ADEV\\)" Date: Tue, 31 Mar 2015 11:40:51 +0200 Subject: lpc32xx: add support for board work_92105 Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB or 128MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) --- arch/arm/include/asm/arch-lpc32xx/clk.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include/asm/arch-lpc32xx/clk.h') diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 2cb5703877..94498695a0 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -71,6 +71,7 @@ struct clk_pm_regs { }; /* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_MASK (0x3 << 7) #define CLK_HCLK_DDRAM_HALF (0x2 << 7) #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) @@ -158,11 +159,15 @@ struct clk_pm_regs { /* SSP Clock Control Register bits */ #define CLK_SSP0_ENABLE_CLOCK (1 << 0) +/* SDRAMCLK register bits */ +#define CLK_SDRAM_DDR_SEL (1 << 1) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); unsigned int get_hclk_clk_rate(void); unsigned int get_periph_clk_div(void); unsigned int get_periph_clk_rate(void); +unsigned int get_sdram_clk_rate(void); #endif /* _LPC32XX_CLK_H */ -- cgit