From dda3b610eee9dcd433627202584ded417327dd51 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Dec 2014 15:30:55 -0800 Subject: arm/ls1021a: Add workaround for DDR erratum A008378 Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-ls102xa/config.h') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da797..a06ef9dcbf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -97,6 +97,7 @@ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #else #error SoC not defined #endif -- cgit