From 5f603761c3de00423cad405e064cd2fc822feab1 Mon Sep 17 00:00:00 2001 From: Praveen Rao Date: Mon, 9 Mar 2015 17:12:06 -0500 Subject: ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870 This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao Signed-off-by: Angela Stegmaier Signed-off-by: Nishanth Menon Tested-by: Matt Porter Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-omap5/sys_proto.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/arch-omap5/sys_proto.h') diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 103830319a..ea84665f5b 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -66,4 +66,7 @@ static inline u32 usec_to_32k(u32 usec) { return div_round_up(32768 * usec, 1000000); } + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + #endif -- cgit