From c541bfda2f88ea5afd258c68d7cb7300dc76c98f Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 28 Nov 2019 15:27:52 +0100 Subject: rockchip: px30: Add support for using UART3 as debug UART Some generic PX30 SoMs found in the wild use UART3 as their debug output instead of UART2 (used for MMC) and UART5. Make it possible to use UART3 as early debug output, with the associated clock and pinmux configuration. Two sets of output pins are supported (M0/M1). Future users should also note that the pinmux default in the dts is to use the M1 pins while the Kconfig option takes M0 as a default. Signed-off-by: Paul Kocialkowski Reviewed-by: Kever Yang Reviewed-by: Heiko Stuebner --- arch/arm/include/asm/arch-rockchip/cru_px30.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/include/asm/arch-rockchip/cru_px30.h') diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h index 7d9fd181ac..798444ae49 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -357,6 +357,25 @@ enum { UART2_DIVNP5_SHIFT = 0, UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, + /* CRU_CLK_SEL40_CON */ + UART3_PLL_SEL_SHIFT = 14, + UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT, + UART3_PLL_SEL_GPLL = 0, + UART3_PLL_SEL_24M, + UART3_PLL_SEL_480M, + UART3_PLL_SEL_NPLL, + UART3_DIV_CON_SHIFT = 0, + UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT, + + /* CRU_CLK_SEL41_CON */ + UART3_CLK_SEL_SHIFT = 14, + UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT, + UART3_CLK_SEL_UART3 = 0, + UART3_CLK_SEL_UART3_NP5, + UART3_CLK_SEL_UART3_FRAC, + UART3_DIVNP5_SHIFT = 0, + UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT, + /* CRU_CLK_SEL46_CON */ UART5_PLL_SEL_SHIFT = 14, UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, -- cgit