From bad5188be2e9ef233d581a00b0dc2c8e6487b50d Mon Sep 17 00:00:00 2001 From: Michael Kurz Date: Sun, 22 Jan 2017 16:04:24 +0100 Subject: ARM: stm32: cleanup stm32f7 files Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - use rcc struct instead of macro additions Add missing stm32f7 register in rcc struct Signed-off-by: Michael Kurz Acked-by: Vikas MANOCHA --- arch/arm/include/asm/arch-stm32f7/fmc.h | 6 ++-- arch/arm/include/asm/arch-stm32f7/gpt.h | 6 ++-- arch/arm/include/asm/arch-stm32f7/rcc.h | 50 +++++++++++++++++++------------ arch/arm/include/asm/arch-stm32f7/stm32.h | 12 ++++++-- 4 files changed, 46 insertions(+), 28 deletions(-) (limited to 'arch/arm/include/asm/arch-stm32f7') diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h index 7dd5077d0c..d61a86fcf1 100644 --- a/arch/arm/include/asm/arch-stm32f7/fmc.h +++ b/arch/arm/include/asm/arch-stm32f7/fmc.h @@ -58,12 +58,12 @@ struct stm32_fmc_regs { #define FMC_SDCMR_MODE_SELFREFRESH 5 #define FMC_SDCMR_MODE_POWERDOWN 6 -#define FMC_SDCMR_BANK_1 (1 << 4) -#define FMC_SDCMR_BANK_2 (1 << 3) +#define FMC_SDCMR_BANK_1 BIT(4) +#define FMC_SDCMR_BANK_2 BIT(3) #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 -#define FMC_SDSR_BUSY (1 << 5) +#define FMC_SDSR_BUSY BIT(5) #define FMC_BUSY_WAIT() do { \ __asm__ __volatile__ ("dsb" : : : "memory"); \ diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h index 903bdf6314..e9e0c142e0 100644 --- a/arch/arm/include/asm/arch-stm32f7/gpt.h +++ b/arch/arm/include/asm/arch-stm32f7/gpt.h @@ -38,8 +38,8 @@ struct gpt_regs *const gpt1_regs_ptr = (struct gpt_regs *)TIM2_BASE; /* Timer control1 register */ -#define GPT_CR1_CEN 0x0001 -#define GPT_MODE_AUTO_RELOAD (1 << 7) +#define GPT_CR1_CEN BIT(0) +#define GPT_MODE_AUTO_RELOAD BIT(7) /* Auto reload register for free running config */ #define GPT_FREE_RUNNING 0xFFFFFFFF @@ -48,6 +48,6 @@ struct gpt_regs *const gpt1_regs_ptr = #define CONFIG_STM32_HZ 1000 /* Timer Event Generation registers */ -#define TIM_EGR_UG (1 << 0) +#define TIM_EGR_UG BIT(0) #endif diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h index 8bfb7b6628..184c366d9d 100644 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -34,31 +34,43 @@ #define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */ #define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */ #define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */ +/* + * RCC AHB1ENR specific definitions + */ +#define RCC_AHB1ENR_GPIO_A_EN BIT(0) +#define RCC_AHB1ENR_GPIO_B_EN BIT(1) +#define RCC_AHB1ENR_GPIO_C_EN BIT(2) +#define RCC_AHB1ENR_GPIO_D_EN BIT(3) +#define RCC_AHB1ENR_GPIO_E_EN BIT(4) +#define RCC_AHB1ENR_GPIO_F_EN BIT(5) +#define RCC_AHB1ENR_GPIO_G_EN BIT(6) +#define RCC_AHB1ENR_GPIO_H_EN BIT(7) +#define RCC_AHB1ENR_GPIO_I_EN BIT(8) +#define RCC_AHB1ENR_GPIO_J_EN BIT(9) +#define RCC_AHB1ENR_GPIO_K_EN BIT(10) +#define RCC_AHB1ENR_ETHMAC_EN BIT(25) +#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) +#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) +#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28) -#define RCC_APB1ENR_TIM2EN (1 << 0) -#define RCC_APB1ENR_PWREN (1 << 28) +/* + * RCC AHB3ENR specific definitions + */ +#define RCC_AHB3ENR_FMC_EN BIT(0) /* - * RCC USART specific definitions + * RCC APB1ENR specific definitions */ -#define RCC_ENR_USART1EN (1 << 4) -#define RCC_ENR_USART2EN (1 << 17) -#define RCC_ENR_USART3EN (1 << 18) -#define RCC_ENR_USART6EN (1 << 5) +#define RCC_APB1ENR_TIM2EN BIT(0) +#define RCC_APB1ENR_USART2EN BIT(17) +#define RCC_APB1ENR_USART3EN BIT(18) +#define RCC_APB1ENR_PWREN BIT(28) /* - * RCC GPIO specific definitions + * RCC APB2ENR specific definitions */ -#define RCC_ENR_GPIO_A_EN (1 << 0) -#define RCC_ENR_GPIO_B_EN (1 << 1) -#define RCC_ENR_GPIO_C_EN (1 << 2) -#define RCC_ENR_GPIO_D_EN (1 << 3) -#define RCC_ENR_GPIO_E_EN (1 << 4) -#define RCC_ENR_GPIO_F_EN (1 << 5) -#define RCC_ENR_GPIO_G_EN (1 << 6) -#define RCC_ENR_GPIO_H_EN (1 << 7) -#define RCC_ENR_GPIO_I_EN (1 << 8) -#define RCC_ENR_GPIO_J_EN (1 << 9) -#define RCC_ENR_GPIO_K_EN (1 << 10) +#define RCC_APB2ENR_USART1EN BIT(4) +#define RCC_APB2ENR_USART6EN BIT(5) +#define RCC_APB2ENR_SYSCFGEN BIT(14) #endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index de55ae5df1..a425178bc0 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -32,6 +32,7 @@ #define USART1_BASE (APB2_PERIPH_BASE + 0x1000) #define USART6_BASE (APB2_PERIPH_BASE + 0x1400) +#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800) #define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) #define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) @@ -62,7 +63,7 @@ enum clock { CLOCK_APB1, CLOCK_APB2 }; -#define STM32_BUS_MASK 0xFFFF0000 +#define STM32_BUS_MASK GENMASK(31, 16) struct stm32_rcc_regs { u32 cr; /* RCC clock control */ @@ -95,11 +96,16 @@ struct stm32_rcc_regs { u32 rsv6[2]; u32 sscgr; /* RCC spread spectrum clock generation */ u32 plli2scfgr; /* RCC PLLI2S configuration */ - u32 pllsaicfgr; - u32 dckcfgr; + u32 pllsaicfgr; /* PLLSAI configuration */ + u32 dckcfgr; /* dedicated clocks configuration register */ }; #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) +struct stm32_rcc_ext_f7_regs { + u32 dckcfgr2; /* dedicated clocks configuration register */ +}; +#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs))) + struct stm32_pwr_regs { u32 cr1; /* power control register 1 */ u32 csr1; /* power control/status register 2 */ -- cgit