From c13f60d92a1c31c131a53ff8e994e4c8eebb8311 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 25 Jan 2015 12:10:48 +0100 Subject: sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig option And use this to set the GMAC Transmit Clock Delay Chain value on Banana boards, rather then keying of CONFIG_TARGET_FOO. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/arch-sunxi/clock_sun4i.h') diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 05fbad3e11..d297ed0f73 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -305,6 +305,8 @@ struct sunxi_ccm_reg { #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -- cgit From f388a26d1132dae7ffe123cd7bd9adf78d4f7b57 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 19 Feb 2015 14:46:44 +0100 Subject: sunxi: Fix sun5i mbus speed when booting old kernels Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, halving the mbus frequency, so set it to 300 MHz ourselves and base the mbus divider on that. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/include/asm/arch-sunxi/clock_sun4i.h') diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index d297ed0f73..c28ee0528f 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -144,7 +144,16 @@ struct sunxi_ccm_reg { #define PLL1_CFG_DEFAULT 0xa1005000 +#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I +/* + * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, + * halving the mbus frequency, so set it to 300 MHz ourselves and base the + * mbus divider on that. + */ +#define PLL6_CFG_DEFAULT 0xa1009900 +#else #define PLL6_CFG_DEFAULT 0xa1009911 +#endif /* nand clock */ #define NAND_CLK_SRC_OSC24 0 -- cgit