From e296995767e645ed047bcbec90923297a24d4d5a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 21 Mar 2014 12:28:54 -0600 Subject: ARM: tegra: pinctrl: remove duplication Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 189 +++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 arch/arm/include/asm/arch-tegra/pinmux.h (limited to 'arch/arm/include/asm/arch-tegra/pinmux.h') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h new file mode 100644 index 0000000000..e97fffdcf8 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2010-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_PINMUX_H_ +#define _TEGRA_PINMUX_H_ + +#include + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, +}; + +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; + +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; + +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; + +#ifdef TEGRA_PMX_HAS_RCV_SEL +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +#endif /* TEGRA_PMX_HAS_RCV_SEL */ +#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pingroup_config { + enum pmux_pingrp pingroup; /* pin group PINGRP_... */ + enum pmux_func func; /* function to assign FUNC_... */ + enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ + enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC + enum pmux_pin_io io; /* input or output PMUX_PIN_... */ + enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ + enum pmux_pin_od od; /* open-drain or push-pull driver */ + enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ +#ifdef TEGRA_PMX_HAS_RCV_SEL + enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ + /* VIL/VIH receivers */ +#endif +#endif +}; + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set a pin group to tristate or normal */ +void pinmux_set_tristate(enum pmux_pingrp pin, int enable); + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); +#endif + +/* Set the complete configuration for a pin group */ +void pinmux_config_pingroup(const struct pingroup_config *config); + +/** + * Configure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_table(const struct pingroup_config *config, int len); + +#ifdef TEGRA_PMX_HAS_PADGRPS + +#define PGRP_SLWF_MIN 0 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWF_NONE -1 + +#define PGRP_SLWR_MIN 0 +#define PGRP_SLWR_MAX 3 +#define PGRP_SLWR_NONE -1 + +#define PGRP_DRVUP_MIN 0 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVUP_NONE -1 + +#define PGRP_DRVDN_MIN 0 +#define PGRP_DRVDN_MAX 127 +#define PGRP_DRVDN_NONE -1 + +/* Defines a pin group cfg's low-power mode select */ +enum pgrp_lpmd { + PGRP_LPMD_X8 = 0, + PGRP_LPMD_X4, + PGRP_LPMD_X2, + PGRP_LPMD_X, + PGRP_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pgrp_schmt { + PGRP_SCHMT_DISABLE = 0, + PGRP_SCHMT_ENABLE = 1, + PGRP_SCHMT_NONE = -1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pgrp_hsm { + PGRP_HSM_DISABLE = 0, + PGRP_HSM_ENABLE = 1, + PGRP_HSM_NONE = -1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct padctrl_config { + enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ + int slwf; /* falling edge slew */ + int slwr; /* rising edge slew */ + int drvup; /* pull-up drive strength */ + int drvdn; /* pull-down drive strength */ + enum pgrp_lpmd lpmd; /* low-power mode selection */ + enum pgrp_schmt schmt; /* schmidt enable */ + enum pgrp_hsm hsm; /* high-speed mode enable */ +}; + +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void padgrp_config_table(const struct padctrl_config *config, int len); + +#endif /* TEGRA_PMX_HAS_PADGRPS */ + +struct tegra_pingroup_desc { + enum pmux_func funcs[4]; +#if defined(CONFIG_TEGRA20) + u32 ctl_id; + u32 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct tegra_pingroup_desc *tegra_soc_pingroups; + +#endif /* _TEGRA_PINMUX_H_ */ -- cgit From a45fa436854a4116c19dd8794c9b033a3cf117bc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 21 Mar 2014 12:28:55 -0600 Subject: ARM: tegra: reduce public pinmux API Remove a few unused functions from the pinmux header. They aren't currently used, and removing them prevents any new usage from appearing. This will ease moving to just pinmux_config_table() and padgrp_config_table() in the future. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm/include/asm/arch-tegra/pinmux.h') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index e97fffdcf8..b8d21c1bf9 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -86,9 +86,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); /* Set the pull up/down feature for a pin group */ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); -/* Set a pin group to tristate or normal */ -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - /* Set a pin group to tristate */ void pinmux_tristate_enable(enum pmux_pingrp pin); @@ -100,9 +97,6 @@ void pinmux_tristate_disable(enum pmux_pingrp pin); void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); #endif -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(const struct pingroup_config *config); - /** * Configure a list of pin groups * -- cgit From dfb42fc95df6b5908fb593db9132018233430fe9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 21 Mar 2014 12:28:56 -0600 Subject: ARM: tegra: pinmux naming consistency fixes Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 88 ++++++++++++++++---------------- 1 file changed, 45 insertions(+), 43 deletions(-) (limited to 'arch/arm/include/asm/arch-tegra/pinmux.h') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index b8d21c1bf9..80b804694a 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -63,16 +63,16 @@ enum pmux_pin_rcv_sel { * you can call pinmux_config_pingroup() to configure a pin in one step. Also * available is pinmux_config_table() to configure a list of pins. */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ +struct pmux_pingrp_config { + enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */ + enum pmux_func func; /* function to assign PMUX_FUNC_... */ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ + enum pmux_pin_io io; /* input or output PMUX_PIN_... */ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + enum pmux_pin_od od; /* open-drain or push-pull driver */ + enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ #ifdef TEGRA_PMX_HAS_RCV_SEL enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ /* VIL/VIH receivers */ @@ -103,61 +103,62 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); * @param config List of config items * @param len Number of config items in list */ -void pinmux_config_table(const struct pingroup_config *config, int len); +void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, + int len); -#ifdef TEGRA_PMX_HAS_PADGRPS +#ifdef TEGRA_PMX_HAS_DRVGRPS -#define PGRP_SLWF_MIN 0 -#define PGRP_SLWF_MAX 3 -#define PGRP_SLWF_NONE -1 +#define PMUX_SLWF_MIN 0 +#define PMUX_SLWF_MAX 3 +#define PMUX_SLWF_NONE -1 -#define PGRP_SLWR_MIN 0 -#define PGRP_SLWR_MAX 3 -#define PGRP_SLWR_NONE -1 +#define PMUX_SLWR_MIN 0 +#define PMUX_SLWR_MAX 3 +#define PMUX_SLWR_NONE -1 -#define PGRP_DRVUP_MIN 0 -#define PGRP_DRVUP_MAX 127 -#define PGRP_DRVUP_NONE -1 +#define PMUX_DRVUP_MIN 0 +#define PMUX_DRVUP_MAX 127 +#define PMUX_DRVUP_NONE -1 -#define PGRP_DRVDN_MIN 0 -#define PGRP_DRVDN_MAX 127 -#define PGRP_DRVDN_NONE -1 +#define PMUX_DRVDN_MIN 0 +#define PMUX_DRVDN_MAX 127 +#define PMUX_DRVDN_NONE -1 /* Defines a pin group cfg's low-power mode select */ -enum pgrp_lpmd { - PGRP_LPMD_X8 = 0, - PGRP_LPMD_X4, - PGRP_LPMD_X2, - PGRP_LPMD_X, - PGRP_LPMD_NONE = -1, +enum pmux_lpmd { + PMUX_LPMD_X8 = 0, + PMUX_LPMD_X4, + PMUX_LPMD_X2, + PMUX_LPMD_X, + PMUX_LPMD_NONE = -1, }; /* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pgrp_schmt { - PGRP_SCHMT_DISABLE = 0, - PGRP_SCHMT_ENABLE = 1, - PGRP_SCHMT_NONE = -1, +enum pmux_schmt { + PMUX_SCHMT_DISABLE = 0, + PMUX_SCHMT_ENABLE = 1, + PMUX_SCHMT_NONE = -1, }; /* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pgrp_hsm { - PGRP_HSM_DISABLE = 0, - PGRP_HSM_ENABLE = 1, - PGRP_HSM_NONE = -1, +enum pmux_hsm { + PMUX_HSM_DISABLE = 0, + PMUX_HSM_ENABLE = 1, + PMUX_HSM_NONE = -1, }; /* * This defines the configuration for a pin group's pad control config */ -struct padctrl_config { - enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ +struct pmux_drvgrp_config { + enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */ int slwf; /* falling edge slew */ int slwr; /* rising edge slew */ int drvup; /* pull-up drive strength */ int drvdn; /* pull-down drive strength */ - enum pgrp_lpmd lpmd; /* low-power mode selection */ - enum pgrp_schmt schmt; /* schmidt enable */ - enum pgrp_hsm hsm; /* high-speed mode enable */ + enum pmux_lpmd lpmd; /* low-power mode selection */ + enum pmux_schmt schmt; /* schmidt enable */ + enum pmux_hsm hsm; /* high-speed mode enable */ }; /** @@ -166,11 +167,12 @@ struct padctrl_config { * @param config List of config items * @param len Number of config items in list */ -void padgrp_config_table(const struct padctrl_config *config, int len); +void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, + int len); -#endif /* TEGRA_PMX_HAS_PADGRPS */ +#endif /* TEGRA_PMX_HAS_DRVGRPS */ -struct tegra_pingroup_desc { +struct pmux_pingrp_desc { enum pmux_func funcs[4]; #if defined(CONFIG_TEGRA20) u32 ctl_id; @@ -178,6 +180,6 @@ struct tegra_pingroup_desc { #endif /* CONFIG_TEGRA20 */ }; -extern const struct tegra_pingroup_desc *tegra_soc_pingroups; +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; #endif /* _TEGRA_PINMUX_H_ */ -- cgit From d381294aef4a5b6ddeda3685519330a5b73d884f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 21 Mar 2014 15:58:03 -0600 Subject: ARM: tegra: pack pinmux data tables tighter Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 42 ++++++++++++++++---------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm/include/asm/arch-tegra/pinmux.h') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 80b804694a..035159d665 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -64,18 +64,18 @@ enum pmux_pin_rcv_sel { * available is pinmux_config_table() to configure a list of pins. */ struct pmux_pingrp_config { - enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */ - enum pmux_func func; /* function to assign PMUX_FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ + u32 pingrp:16; /* pin group PMUX_PINGRP_... */ + u32 func:8; /* function to assign PMUX_FUNC_... */ + u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ + u32 tristate:2; /* tristate or normal PMUX_TRI_... */ #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + u32 io:2; /* input or output PMUX_PIN_... */ + u32 lock:2; /* lock enable/disable PMUX_PIN... */ + u32 od:2; /* open-drain or push-pull driver */ + u32 ioreset:2; /* input/output reset PMUX_PIN... */ #ifdef TEGRA_PMX_HAS_RCV_SEL - enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ - /* VIL/VIH receivers */ + u32 rcv_sel:2; /* select between High and Normal */ + /* VIL/VIH receivers */ #endif #endif }; @@ -151,14 +151,14 @@ enum pmux_hsm { * This defines the configuration for a pin group's pad control config */ struct pmux_drvgrp_config { - enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pmux_lpmd lpmd; /* low-power mode selection */ - enum pmux_schmt schmt; /* schmidt enable */ - enum pmux_hsm hsm; /* high-speed mode enable */ + u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ + u32 slwf:3; /* falling edge slew */ + u32 slwr:3; /* rising edge slew */ + u32 drvup:8; /* pull-up drive strength */ + u32 drvdn:8; /* pull-down drive strength */ + u32 lpmd:3; /* low-power mode selection */ + u32 schmt:2; /* schmidt enable */ + u32 hsm:2; /* high-speed mode enable */ }; /** @@ -173,10 +173,10 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_HAS_DRVGRPS */ struct pmux_pingrp_desc { - enum pmux_func funcs[4]; + u8 funcs[4]; #if defined(CONFIG_TEGRA20) - u32 ctl_id; - u32 pull_id; + u8 ctl_id; + u8 pull_id; #endif /* CONFIG_TEGRA20 */ }; -- cgit