From 6c81a93db700021614c6ae150f8c1c995173201f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 11 Mar 2014 18:43:59 +0100 Subject: arm: vf610: add enet1 support This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secondary Ethernet (enet1) MAC RMII1 base address definition - RMII1 iomux definitions - VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for internal (e.g. crystal-less) Ethernet clocking. Signed-off-by: Marcel Ziswiler [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner --- arch/arm/include/asm/arch-vf610/imx-regs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-vf610/imx-regs.h') diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b8c877f939..c2f9761846 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -85,6 +85,7 @@ #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) /* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG -- cgit