From 575001e40c9d10e63f2924649098e7c07d3985c7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 13 Oct 2010 12:16:35 +0200 Subject: MX51: Add IPU driver for video support The patch is a porting of the IPU Linux driver developed by Freescale to have framebuffer functionalities in u-boot. The port is based on kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f, as delivered by Freescale [i.MX BSP]. Most features are dropped from the original driver and only LCD support is the goal of this porting. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx5/crm_regs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 14aa231a5b..4ed8eb31c8 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -189,4 +189,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) + +/* Define the bits in register CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR5_CG5_OFFSET 10 + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) + #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ -- cgit From 25ddd1fb0a2281b182529afbc8fda5de2dc16d96 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 26 Oct 2010 14:34:52 +0200 Subject: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk Acked-by: Kumar Gala --- arch/arm/include/asm/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 6dae4328e6..5438ebc5fb 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -30,7 +30,7 @@ * global variables during system initialization (until we have set * up the memory controller so that we can use RAM). * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) + * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) */ typedef struct global_data { -- cgit From 9b8081a4525b3b2b655ba71fdeea1cb265d413e8 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Thu, 28 Oct 2010 01:47:24 +0400 Subject: arm/pxa: remove unused arch-pxa/macro.h Signed-off-by: Mikhail Kshevetskiy --- arch/arm/include/asm/arch-pxa/macro.h | 328 ---------------------------------- 1 file changed, 328 deletions(-) delete mode 100644 arch/arm/include/asm/arch-pxa/macro.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h deleted file mode 100644 index 85958dd32d..0000000000 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * arch/arm/include/asm/arch-pxa/macro.h - * - * Copyright (C) 2010 Marek Vasut - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_PXA_MACRO_H__ -#define __ASM_ARCH_PXA_MACRO_H__ -#ifdef __ASSEMBLY__ - -#include -#include - -/* - * This macro performs a 32bit write to a memory location and makes sure the - * write operation really happened by performing a read back. - * - * Clobbered regs: r4, r5 - */ -.macro write32rb addr, data - ldr r4, =\addr - ldr r5, =\data - str r5, [r4] - ldr r5, [r4] -.endm - -/* - * This macro waits according to OSCR incrementation - * - * Clobbered regs: r4, r5, r6 - */ -.macro pxa_wait_ticks ticks - ldr r4, =OSCR - mov r5, #0 - str r5, [r4] - ldr r5, =\ticks -1: - ldr r6, [r4] - cmp r5, r6 - bgt 1b -.endm - -/* - * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU - * - * Clobbered regs: r4, r5 - */ -.macro pxa_gpio_setup - write32 GPSR0, CONFIG_SYS_GPSR0_VAL - write32 GPSR1, CONFIG_SYS_GPSR1_VAL - write32 GPSR2, CONFIG_SYS_GPSR2_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GPSR3, CONFIG_SYS_GPSR3_VAL -#endif - - write32 GPCR0, CONFIG_SYS_GPCR0_VAL - write32 GPCR1, CONFIG_SYS_GPCR1_VAL - write32 GPCR2, CONFIG_SYS_GPCR2_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GPCR3, CONFIG_SYS_GPCR3_VAL -#endif - - write32 GPDR0, CONFIG_SYS_GPDR0_VAL - write32 GPDR1, CONFIG_SYS_GPDR1_VAL - write32 GPDR2, CONFIG_SYS_GPDR2_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GPDR3, CONFIG_SYS_GPDR3_VAL -#endif - - write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL - write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL - write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL - write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL - write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL - write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL - write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL -#endif - - write32 PSSR, CONFIG_SYS_PSSR_VAL -.endm - -/* - * This macro sets up the Memory controller of the PXA2xx CPU - * - * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE - * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not - * use this regs for other purpose inside this macro. - * - * Clobbered regs: r3, r4, r5, r6, r7 - */ -.macro pxa_mem_setup - /* This comes handy when setting MDREFR */ - ldr r3, =MEMC_BASE - - /* - * 1) Initialize Asynchronous static memory controller - */ - - /* MSC0: nCS(0,1) */ - write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL - /* MSC1: nCS(2,3) */ - write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL - /* MSC2: nCS(4,5) */ - write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL - - /* - * 2) Initialize Card Interface - */ - - /* MECR: Memory Expansion Card Register */ - write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL - /* MCMEM0: Card Interface slot 0 timing */ - write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL - /* MCMEM1: Card Interface slot 1 timing */ - write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL - - /* - * 3) Configure Fly-By DMA register - */ - - write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL - - /* - * 4) Initialize Timing for Sync Memory (SDCLK0) - */ - - /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. - */ - ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r7, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ - - orr r5, #MDREFR_K0RUN - orr r5, #MDREFR_SLFRSH - bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN - - str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] - - /* - * 5) Initialize Synchronous Static Memory (Flash/Peripherals) - */ - - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. - */ - write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL - - /* - * 6) Initialize SDRAM - */ - - bic r7, #MDREFR_SLFRSH - str r7, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] - - orr r7, #MDREFR_E1PIN - str r7, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] - - /* - * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure - * but not enable each SDRAM partition pair. - */ - - /* Fetch platform value of MDCNFG */ - ldr r4, =CONFIG_SYS_MDCNFG_VAL - /* Disable all sdram banks */ - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) - /* Write initial value of MDCNFG, w/o enabling sdram banks */ - str r4, [r3, #MDCNFG_OFFSET] - ldr r4, [r3, #MDCNFG_OFFSET] - - /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ - pxa_wait_ticks 0x300 - - /* - * 8) Trigger a number (usually 8) refresh cycles by attempting - * non-burst read or write accesses to disabled SDRAM, as commonly - * specified in the power up sequence documented in SDRAM data - * sheets. The address(es) used for this purpose must not be - * cacheable. - */ - - ldr r4, =CONFIG_SYS_DRAM_BASE -.rept 9 - str r5, [r4] -.endr - - /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). - */ - - ldr r5, =CONFIG_SYS_MDCNFG_VAL - ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3) - and r5, r5, r4 - ldr r4, [r3, #MDCNFG_OFFSET] - orr r4, r4, r5 - str r4, [r3, #MDCNFG_OFFSET] - ldr r4, [r3, #MDCNFG_OFFSET] - - /* - * 10) Write MDMRS. - */ - - ldr r4, =CONFIG_SYS_MDMRS_VAL - str r4, [r3, #MDMRS_OFFSET] - ldr r4, [r3, #MDMRS_OFFSET] - - /* - * 11) Enable APD - */ - - ldr r4, [r3, #MDREFR_OFFSET] - and r7, r7, #MDREFR_APD - orr r4, r4, r7 - str r4, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] -.endm - -/* - * This macro tests if the CPU woke up from sleep and eventually resumes - * - * Clobbered regs: r4, r5 - */ -.macro pxa_wakeup - ldr r4, =RCSR - ldr r5, [r4] - and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) - str r5, [r4] - teq r5, #RCSR_SMR - - bne pxa_wakeup_exit - - ldr r4, =PSSR - mov r5, #PSSR_PH - str r5, [r4] - - ldr r4, =PSPR - ldr pc, [r4] -pxa_wakeup_exit: -.endm - -/* - * This macro disables all interupts on PXA2xx/PXA3xx CPU - * - * Clobbered regs: r4, r5 - */ -.macro pxa_intr_setup - write32 ICLR, 0 - write32 ICMR, 0 -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 ICLR2, 0 - write32 ICMR2, 0 -#endif -.endm - -/* - * This macro configures clock on PXA2xx/PXA3xx CPU - * - * Clobbered regs: r4, r5 - */ -.macro pxa_clock_setup - /* Disable the peripheral clocks, and set the core clock frequency */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - write32 CKEN, CONFIG_SYS_CKEN - - /* Write CCCR */ - write32 CCCR, CONFIG_SYS_CCCR - -#ifdef CONFIG_RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - write32 OSCC, #OSCC_OON - ldr r4, =OSCC - - /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */ -2: - ldr r5, [r4] - ands r5, r5, #1 - beq 2b -#endif -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_PXA_MACRO_H__ */ -- cgit From 81129d07a0e9f6e28029170b082d6f8810f72712 Mon Sep 17 00:00:00 2001 From: Matthias Weisser Date: Wed, 27 Oct 2010 16:34:38 +0200 Subject: imx25: Fix reset This patch fixes the reset command on imx25. The watchdog registers are 16 bits in size and not 32. This patch also adds the service register codes as constants. Signed-off-by: Matthias Weisser --- arch/arm/include/asm/arch-mx25/imx-regs.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index f709bd8e0e..f5a2929e22 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -108,11 +108,11 @@ struct gpt_regs { /* Watchdog Timer (WDOG) registers */ struct wdog_regs { - u32 wcr; /* Control */ - u32 wsr; /* Service */ - u32 wrsr; /* Reset Status */ - u32 wicr; /* Interrupt Control */ - u32 wmcr; /* Misc Control */ + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Misc Control */ }; /* IIM control registers */ @@ -308,7 +308,9 @@ struct iim_regs { #define GPT_CTRL_TEN 1 /* Timer enable */ /* WDOG enable */ -#define WCR_WDE 0x04 +#define WCR_WDE 0x04 +#define WSR_UNLOCK1 0x5555 +#define WSR_UNLOCK2 0xAAAA /* FUSE bank offsets */ #define IIM0_MAC 0x1a -- cgit From 1ab027cbf6536f40348699a7b7bfa8bbedf88c8e Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 28 Oct 2010 10:13:15 +0800 Subject: mx51evk: support new relocation scheme This patch is to fix build breakage and support new relocation scheme for mx51evk. - Correct IRAM base address and add size definition The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than 0x1FFE8000 which is for older revision. - Include imx-regs.h in mx51evk.h Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be referred to. - Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE They are used to define init RAM layout. - Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been buried by Wolfgang's commit below 25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value Signed-off-by: Shawn Guo --- arch/arm/include/asm/arch-mx5/imx-regs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 3ddda401f3..0b6249a9b8 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -26,7 +26,8 @@ /* * IRAM */ -#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ +#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define IRAM_SIZE 0x00020000 /* 128 KB */ /* * Graphics Memory of GPU */ -- cgit From 2e5167ccad93ca9cfa6a2acfab5e4785418e477e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 28 Oct 2010 20:00:11 +0200 Subject: Replace CONFIG_RELOC_FIXUP_WORKS by CONFIG_NEEDS_MANUAL_RELOC By now, the majority of architectures have working relocation support, so the few remaining architectures have become exceptions. To make this more obvious, we make working relocation now the default case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC. Signed-off-by: Wolfgang Denk Tested-by: Heiko Schocher Tested-by: Reinhard Meyer --- arch/arm/include/asm/config.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 4124f0a992..c60dba26bf 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -21,9 +21,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -/* Relocation to SDRAM works on all ARM boards */ -#define CONFIG_RELOC_FIXUP_WORKS - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #endif -- cgit From a9aa3926295df759306258e5e24cace414f53b67 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 28 Oct 2010 20:35:36 +0200 Subject: Drop support for CONFIG_SYS_ARM_WITHOUT_RELOC When this define was introduced, the idea was to provide a soft migration path for ARM boards to get adapted to the new relocation support. However, other recent changes led to a different implementation (ELF relocation), where this no longer works. By now CONFIG_SYS_ARM_WITHOUT_RELOC does not only not help any more, but it actually hurts because it obfuscates the actual code by sprinkling it with lots of dead and non-working debris. So let's make a clean cut and drop CONFIG_SYS_ARM_WITHOUT_RELOC. Signed-off-by: Wolfgang Denk Tested-by: Heiko Schocher Tested-by: Reinhard Meyer --- arch/arm/include/asm/global_data.h | 2 -- arch/arm/include/asm/u-boot-arm.h | 6 ------ 2 files changed, 8 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 5438ebc5fb..ada3fbb641 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -61,7 +61,6 @@ typedef struct global_data { unsigned long tbu; unsigned long long timer_reset_value; #endif -#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ unsigned long mon_len; /* monitor len */ @@ -70,7 +69,6 @@ typedef struct global_data { unsigned long reloc_off; #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) unsigned long tlb_addr; -#endif #endif void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 4ac4f612e9..33973a32e0 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -34,16 +34,12 @@ extern ulong _bss_start_ofs; /* BSS start relative to _start */ extern ulong _bss_end_ofs; /* BSS end relative to _start */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ -#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) -extern ulong _armboot_start_ofs; /* code start */ -#else extern ulong _TEXT_BASE; /* code start */ extern ulong _datarel_start_ofs; extern ulong _datarelrolocal_start_ofs; extern ulong _datarellocal_start_ofs; extern ulong _datarelro_start_ofs; extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */ -#endif /* cpu/.../cpu.c */ int cpu_init(void); @@ -56,9 +52,7 @@ int arch_misc_init(void); /* board/.../... */ int board_init(void); int dram_init (void); -#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) void dram_init_banksize (void); -#endif void setup_serial_tag (struct tag **params); void setup_revision_tag (struct tag **params); -- cgit From 33825ec1a48b279a5e825b1df4eda8b5da1fb34a Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Mon, 25 Oct 2010 17:56:23 +0200 Subject: AT91: add 2nd SPI to 9260/9XE/9G20 Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/hardware.h | 1 + arch/arm/include/asm/arch-at91/memory-map.h | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index f5f80e0b1b..6b44d61207 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -23,6 +23,7 @@ #include #define AT91_BASE_MCI AT91SAM9260_BASE_MCI #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 +#define AT91_BASE_SPI1 AT91SAM9260_BASE_SPI1 #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) diff --git a/arch/arm/include/asm/arch-at91/memory-map.h b/arch/arm/include/asm/arch-at91/memory-map.h index f605f37fd2..d489fa2157 100644 --- a/arch/arm/include/asm/arch-at91/memory-map.h +++ b/arch/arm/include/asm/arch-at91/memory-map.h @@ -31,5 +31,6 @@ #define USART2_BASE AT91_USART2 #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) #define SPI0_BASE AT91_BASE_SPI +#define SPI1_BASE AT91_BASE_SPI1 #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ -- cgit From 7d44af08b823b9f83e328a4bc2192ab7cbb31e9a Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Mon, 25 Oct 2010 17:56:11 +0200 Subject: AT91: add header file for the Shutdown Controller and SHDWN address entry in at91sam9260.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91_shdwn.h | 38 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/at91sam9260.h | 1 + 2 files changed, 39 insertions(+) create mode 100644 arch/arm/include/asm/arch-at91/at91_shdwn.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h new file mode 100644 index 0000000000..874f988700 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_shdwn.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * Shutdown Controller + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_SHDWN_H +#define AT91_SHDWN_H + +#ifndef __ASSEMBLY__ + +struct at91_shdwn { + u32 cr; /* Control Rer. WO */ + u32 mr; /* Mode Register RW 0x00000003 */ + u32 sr; /* Status Register RO 0x00000000 */ +}; + +#endif /* __ASSEMBLY__ */ + +#define AT91_SHDW_CR_KEY 0xa5000000 +#define AT91_SHDW_CR_SHDW 0x00000001 + +#define AT91_SHDW_MR_RTTWKEN 0x00010000 +#define AT91_SHDW_MR_CPTWK0 0x000000f0 +#define AT91_SHDW_MR_WKMODE0H2L 0x00000002 +#define AT91_SHDW_MR_WKMODE0L2H 0x00000001 + +#define AT91_SHDW_SR_RTTWK 0x00010000 +#define AT91_SHDW_SR_WAKEUP0 0x00000001 + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index cb34a94a3b..7fd60b74ff 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -56,6 +56,7 @@ #define AT91_PIO_BASE 0xfffff400 #define AT91_PMC_BASE 0xfffffc00 #define AT91_RSTC_BASE 0xfffffd00 +#define AT91_SHDWN_BASE 0xfffffd10 #define AT91_RTT_BASE 0xfffffd20 #define AT91_PIT_BASE 0xfffffd30 #define AT91_WDT_BASE 0xfffffd40 -- cgit