From 27c4a3318f716cce0a23248317534bda7792230b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 19 Apr 2012 08:04:39 +0000 Subject: tegra: Correct PLL access in ap20.c and clock.c Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra2/clock.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 1d3ae38644..ff83bbf293 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -186,8 +186,9 @@ enum periph_id { /* Mask value for a clock (within PERIPH_REG(id)) */ #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) -/* return 1 if a PLL ID is in range */ -#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 -- cgit