From 70e21b06425ad6e1e90931333a704a600941cfff Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Mon, 28 Mar 2016 16:16:01 -0500 Subject: armv8: LSCH2 early and final mmu needs matching NS attribute When switching between the early and final mmu tables, the stack will get corrupted if the Non-Secure attribute is different. For ls1043a, this issue is currently masked because flush_dcache_all is called before the switch when CONFIG_SYS_DPAA_FMAN is defined. Signed-off-by: Ed Swarthout Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index f75faa6ffe..905494232f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -157,9 +157,11 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif }; @@ -245,7 +247,8 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -256,7 +259,8 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif }; #endif -- cgit From 96077896ee01d890d2758ce39aaf81af5f60dc59 Mon Sep 17 00:00:00 2001 From: Vincent Siles Date: Tue, 29 Mar 2016 09:41:16 +0200 Subject: arm: ls102xa: Fix order of CSU indexes in ns_access.h This patch aims to fix the order of CSU slave index for the LS1021a board. Signed-off-by: Vincent Siles Reviewed-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/ns_access.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index a921fb6d14..44acfd2967 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -82,12 +82,12 @@ enum csu_cslx_ind { CSU_CSLX_FTM5, CSU_CSLX_FTM8, CSU_CSLX_FTM7, - CSU_CSLX_COP_DCSR, CSU_CSLX_EPU, - CSU_CSLX_GDI, + CSU_CSLX_COP_DCSR, CSU_CSLX_DDI, + CSU_CSLX_GDI, CSU_CSLX_RESERVED1, - CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_USB3_PHY = 116, CSU_CSLX_RESERVED2, CSU_CSLX_MAX, }; -- cgit From 3c1d218a1d3048fb576677c47eab43049d0b7778 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 4 Apr 2016 11:41:26 -0700 Subject: armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun CC: Prabhakar Kushwaha Reviewed-by: Prabhakar Kushwaha --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 ++------- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ arch/arm/include/asm/fsl_secure_boot.h | 12 +++++------- 5 files changed, 12 insertions(+), 16 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ceefe431fd..10d17b2bef 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -23,16 +23,11 @@ */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#ifdef CONFIG_LS2080A -#define CONFIG_NUM_DDR_CONTROLLERS 2 -#endif -#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR -#endif +#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 905494232f..702b9faabd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -206,7 +206,7 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d1fbde79d5..f71c2c1773 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 56989e1e08..831d81764e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -94,4 +94,7 @@ void cpu_name(char *name); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 void erratum_a009635(void); #endif + +bool soc_has_dp_ddr(void); +bool soc_has_aiop(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d576f2ef45..53cd7550a0 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -44,15 +44,14 @@ #endif -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit - * Similiarly for LS2080 and LS2085 + * Similiarly for LS2080 */ #define CONFIG_ESBC_ADDR_64BIT #endif -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ "setenv initrd_high 0xcfffffff;" \ @@ -66,12 +65,11 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR and DDR memory map */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 #define CONFIG_BS_ADDR_FLASH 0x583900000 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 -- cgit