From 7b8657e2bd1ffc7a13793f18d0e069f3c9646356 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2013 15:53:44 +0200 Subject: ARM: mxs: Receive r0 and r1 passed from BootROM Make sure value in register r0 and r1 is preserved and passed to the board_init_ll() and mxs_common_spl_init() where it can be processed further. The value in r0 can be configured during the BootStream generation to arbitary value, r1 contains pointer to return value from CALL'd function. This patch also clears the value in r0 before returning to BootROM to make sure the BootROM is not confused by this value. Finally, this patch cleans up some comments in the start.S file. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/include/asm/arch-mxs/sys_proto.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 1038592c92..43c7dd6bf1 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -28,8 +28,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); #include #endif -void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); +void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, + const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size); #endif struct mxs_pair { -- cgit From e24278aff2684ae459353c44fa7ee91c04e67413 Mon Sep 17 00:00:00 2001 From: trem Date: Fri, 6 Sep 2013 17:33:45 +0200 Subject: mx27: add missing constant for mx27 Add some missing constant (chip select, ...) Signed-off-by: Philippe Reynes Signed-off-by: Eric Jarrige Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx27/imx-regs.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index a27145ba28..92c847e44a 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -169,7 +169,7 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; - } bank[1]; + } bank[2]; }; struct fuse_bank0_regs { @@ -209,9 +209,13 @@ struct fuse_bank0_regs { #define IIM_BASE_ADDR IMX_IIM_BASE #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) +#define IMX_NFC_BASE (0xD8000000) #define IMX_ESD_BASE (0xD8001000) #define IMX_WEIM_BASE (0xD8002000) +#define NFC_BASE_ADDR IMX_NFC_BASE + + /* FMCR System Control bit definition*/ #define UART4_RXD_CTL (1 << 25) #define UART4_RTS_CTL (1 << 24) -- cgit From 771f74c3d31a265bae103b2b407286ec03a4589b Mon Sep 17 00:00:00 2001 From: Kuo-Jung Su Date: Mon, 29 Jul 2013 13:51:43 +0800 Subject: arm: dma_alloc_coherent: malloc() -> memalign() Even though the MMU/D-cache is off, some DMA engines still expect strict address alignment. For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet controllers expect the tx/rx descriptors should always be aligned to 16-bytes boundary. Signed-off-by: Kuo-Jung Su CC: Albert ARIBAUD --- arch/arm/include/asm/dma-mapping.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 009863beec..55a4e266a0 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -16,7 +16,7 @@ enum dma_data_direction { static void *dma_alloc_coherent(size_t len, unsigned long *handle) { - *handle = (unsigned long)malloc(len); + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); return (void *)*handle; } -- cgit From aeef2b090d0d982f83dd9a64a22a5e7275dd2939 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 19 Aug 2013 15:01:22 +0900 Subject: ARM: s3c44b0: remove remainders of dead board Because commit 5dc5f36 removed B2 board support, arch/arm/cpu/s3c44b0/* and arch/arm/include/asm/arch-s3c44b0/* are not necessary anymore. Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk Cc: Andrea Scian --- arch/arm/include/asm/arch-s3c44b0/hardware.h | 281 --------------------------- 1 file changed, 281 deletions(-) delete mode 100644 arch/arm/include/asm/arch-s3c44b0/hardware.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h deleted file mode 100644 index 146e265d9a..0000000000 --- a/arch/arm/include/asm/arch-s3c44b0/hardware.h +++ /dev/null @@ -1,281 +0,0 @@ -/********************************************************/ -/* */ -/* Samsung S3C44B0 */ -/* tpu */ -/* */ -/********************************************************/ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define REGBASE 0x01c00000 -#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) -#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) -#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) - - -/*****************************/ -/* CPU Wrapper Registers */ -/*****************************/ - -#define SYSCFG REGL(0x000000) -#define NCACHBE0 REGL(0x000004) -#define NCACHBE1 REGL(0x000008) -#define SBUSCON REGL(0x040000) - -/************************************/ -/* Memory Controller Registers */ -/************************************/ - -#define BWSCON REGL(0x080000) -#define BANKCON0 REGL(0x080004) -#define BANKCON1 REGL(0x080008) -#define BANKCON2 REGL(0x08000c) -#define BANKCON3 REGL(0x080010) -#define BANKCON4 REGL(0x080014) -#define BANKCON5 REGL(0x080018) -#define BANKCON6 REGL(0x08001c) -#define BANKCON7 REGL(0x080020) -#define REFRESH REGL(0x080024) -#define BANKSIZE REGL(0x080028) -#define MRSRB6 REGL(0x08002c) -#define MRSRB7 REGL(0x080030) - -/*********************/ -/* UART Registers */ -/*********************/ - -#define ULCON0 REGL(0x100000) -#define ULCON1 REGL(0x104000) -#define UCON0 REGL(0x100004) -#define UCON1 REGL(0x104004) -#define UFCON0 REGL(0x100008) -#define UFCON1 REGL(0x104008) -#define UMCON0 REGL(0x10000c) -#define UMCON1 REGL(0x10400c) -#define UTRSTAT0 REGL(0x100010) -#define UTRSTAT1 REGL(0x104010) -#define UERSTAT0 REGL(0x100014) -#define UERSTAT1 REGL(0x104014) -#define UFSTAT0 REGL(0x100018) -#define UFSTAT1 REGL(0x104018) -#define UMSTAT0 REGL(0x10001c) -#define UMSTAT1 REGL(0x10401c) -#define UTXH0 REGB(0x100020) -#define UTXH1 REGB(0x104020) -#define URXH0 REGB(0x100024) -#define URXH1 REGB(0x104024) -#define UBRDIV0 REGL(0x100028) -#define UBRDIV1 REGL(0x104028) - -/*******************/ -/* SIO Registers */ -/*******************/ - -#define SIOCON REGL(0x114000) -#define SIODAT REGL(0x114004) -#define SBRDR REGL(0x114008) -#define ITVCNT REGL(0x11400c) -#define DCNTZ REGL(0x114010) - -/********************/ -/* IIS Registers */ -/********************/ - -#define IISCON REGL(0x118000) -#define IISMOD REGL(0x118004) -#define IISPSR REGL(0x118008) -#define IISFIFCON REGL(0x11800c) -#define IISFIF REGW(0x118010) - -/**************************/ -/* I/O Ports Registers */ -/**************************/ - -#define PCONA REGL(0x120000) -#define PDATA REGL(0x120004) -#define PCONB REGL(0x120008) -#define PDATB REGL(0x12000c) -#define PCONC REGL(0x120010) -#define PDATC REGL(0x120014) -#define PUPC REGL(0x120018) -#define PCOND REGL(0x12001c) -#define PDATD REGL(0x120020) -#define PUPD REGL(0x120024) -#define PCONE REGL(0x120028) -#define PDATE REGL(0x12002c) -#define PUPE REGL(0x120030) -#define PCONF REGL(0x120034) -#define PDATF REGL(0x120038) -#define PUPF REGL(0x12003c) -#define PCONG REGL(0x120040) -#define PDATG REGL(0x120044) -#define PUPG REGL(0x120048) -#define SPUCR REGL(0x12004c) -#define EXTINT REGL(0x120050) -#define EXTINTPND REGL(0x120054) - -/*********************************/ -/* WatchDog Timers Registers */ -/*********************************/ - -#define WTCON REGL(0x130000) -#define WTDAT REGL(0x130004) -#define WTCNT REGL(0x130008) - -/*********************************/ -/* A/D Converter Registers */ -/*********************************/ - -#define ADCCON REGL(0x140000) -#define ADCPSR REGL(0x140004) -#define ADCDAT REGL(0x140008) - -/***************************/ -/* PWM Timer Registers */ -/***************************/ - -#define TCFG0 REGL(0x150000) -#define TCFG1 REGL(0x150004) -#define TCON REGL(0x150008) -#define TCNTB0 REGL(0x15000c) -#define TCMPB0 REGL(0x150010) -#define TCNTO0 REGL(0x150014) -#define TCNTB1 REGL(0x150018) -#define TCMPB1 REGL(0x15001c) -#define TCNTO1 REGL(0x150020) -#define TCNTB2 REGL(0x150024) -#define TCMPB2 REGL(0x150028) -#define TCNTO2 REGL(0x15002c) -#define TCNTB3 REGL(0x150030) -#define TCMPB3 REGL(0x150034) -#define TCNTO3 REGL(0x150038) -#define TCNTB4 REGL(0x15003c) -#define TCMPB4 REGL(0x150040) -#define TCNTO4 REGL(0x150044) -#define TCNTB5 REGL(0x150048) -#define TCNTO5 REGL(0x15004c) - -/*********************/ -/* IIC Registers */ -/*********************/ - -#define IICCON REGL(0x160000) -#define IICSTAT REGL(0x160004) -#define IICADD REGL(0x160008) -#define IICDS REGL(0x16000c) - -/*********************/ -/* RTC Registers */ -/*********************/ - -#define RTCCON REGB(0x170040) -#define RTCALM REGB(0x170050) -#define ALMSEC REGB(0x170054) -#define ALMMIN REGB(0x170058) -#define ALMHOUR REGB(0x17005c) -#define ALMDAY REGB(0x170060) -#define ALMMON REGB(0x170064) -#define ALMYEAR REGB(0x170068) -#define RTCRST REGB(0x17006c) -#define BCDSEC REGB(0x170070) -#define BCDMIN REGB(0x170074) -#define BCDHOUR REGB(0x170078) -#define BCDDAY REGB(0x17007c) -#define BCDDATE REGB(0x170080) -#define BCDMON REGB(0x170084) -#define BCDYEAR REGB(0x170088) -#define TICINT REGB(0x17008c) - -/*********************************/ -/* Clock & Power Registers */ -/*********************************/ - -#define PLLCON REGL(0x180000) -#define CLKCON REGL(0x180004) -#define CLKSLOW REGL(0x180008) -#define LOCKTIME REGL(0x18000c) - -/**************************************/ -/* Interrupt Controller Registers */ -/**************************************/ - -#define INTCON REGL(0x200000) -#define INTPND REGL(0x200004) -#define INTMOD REGL(0x200008) -#define INTMSK REGL(0x20000c) -#define I_PSLV REGL(0x200010) -#define I_PMST REGL(0x200014) -#define I_CSLV REGL(0x200018) -#define I_CMST REGL(0x20001c) -#define I_ISPR REGL(0x200020) -#define I_ISPC REGL(0x200024) -#define F_ISPR REGL(0x200038) -#define F_ISPC REGL(0x20003c) - -/********************************/ -/* LCD Controller Registers */ -/********************************/ - -#define LCDCON1 REGL(0x300000) -#define LCDCON2 REGL(0x300004) -#define LCDSADDR1 REGL(0x300008) -#define LCDSADDR2 REGL(0x30000c) -#define LCDSADDR3 REGL(0x300010) -#define REDLUT REGL(0x300014) -#define GREENLUT REGL(0x300018) -#define BLUELUT REGL(0x30001c) -#define DP1_2 REGL(0x300020) -#define DP4_7 REGL(0x300024) -#define DP3_5 REGL(0x300028) -#define DP2_3 REGL(0x30002c) -#define DP5_7 REGL(0x300030) -#define DP3_4 REGL(0x300034) -#define DP4_5 REGL(0x300038) -#define DP6_7 REGL(0x30003c) -#define LCDCON3 REGL(0x300040) -#define DITHMODE REGL(0x300044) - -/*********************/ -/* DMA Registers */ -/*********************/ - -#define ZDCON0 REGL(0x280000) -#define ZDISRC0 REGL(0x280004) -#define ZDIDES0 REGL(0x280008) -#define ZDICNT0 REGL(0x28000c) -#define ZDCSRC0 REGL(0x280010) -#define ZDCDES0 REGL(0x280014) -#define ZDCCNT0 REGL(0x280018) - -#define ZDCON1 REGL(0x280020) -#define ZDISRC1 REGL(0x280024) -#define ZDIDES1 REGL(0x280028) -#define ZDICNT1 REGL(0x28002c) -#define ZDCSRC1 REGL(0x280030) -#define ZDCDES1 REGL(0x280034) -#define ZDCCNT1 REGL(0x280038) - -#define BDCON0 REGL(0x380000) -#define BDISRC0 REGL(0x380004) -#define BDIDES0 REGL(0x380008) -#define BDICNT0 REGL(0x38000c) -#define BDCSRC0 REGL(0x380010) -#define BDCDES0 REGL(0x380014) -#define BDCCNT0 REGL(0x380018) - -#define BDCON1 REGL(0x380020) -#define BDISRC1 REGL(0x380024) -#define BDIDES1 REGL(0x380028) -#define BDICNT1 REGL(0x38002c) -#define BDCSRC1 REGL(0x380030) -#define BDCDES1 REGL(0x380034) -#define BDCCNT1 REGL(0x380038) - - -#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) -#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) -#define INT_DISABLE(n) INTMSK |= (1<<(n)) - -#define HARD_RESET_NOW() - -#endif /* __ASM_ARCH_HARDWARE_H */ -- cgit From 6a0d803c7c9eeee24f579b764eb4bc51ed79eb5e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:44 -0400 Subject: am33xx: Add am33xx_spl_board_init function, call We need to allow for a further call-out in spl_board_init. Call this am33xx_spl_board_init and add a __weak version. This function may be used to scale the MPU frequency up, depending on board needs. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index c6070a3fc9..55f57ac9be 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -42,4 +42,5 @@ u32 wait_on_value(u32, u32, void *, u32); #ifdef CONFIG_NOR_BOOT void enable_norboot_pin_mux(void); #endif +void am33xx_spl_board_init(void); #endif -- cgit From 5287946c0612e55f948b6ccbe2beaaffb78130ef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:45 -0400 Subject: am33xx: Add the efuse_sma CONTROL_MODULE register Starting with PG2.1 we have a register in the CONTROL_MODULE that is set with the package type and maximum supported frequency. Add this, and the relevant mask/values. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 73e6db8998..52fa128af9 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -38,6 +38,16 @@ #define AM335X 0xB944 #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) +#define DEVICE_ID_MASK 0x1FFF + +/* MPU max frequencies */ +#define AM335X_ZCZ_300 0x1FEF +#define AM335X_ZCZ_600 0x1FAF +#define AM335X_ZCZ_720 0x1F2F +#define AM335X_ZCZ_800 0x1E2F +#define AM335X_ZCZ_1000 0x1C2F +#define AM335X_ZCE_300 0x1FDF +#define AM335X_ZCE_600 0x1F9F /* This gives the status of the boot mode pins on the evm */ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ @@ -509,6 +519,8 @@ struct ctrl_dev { unsigned int macid1h; /* offset 0x3c */ unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ + unsigned int resv5[106]; + unsigned int efuse_sma; /* offset 0x1FC */ }; /* gmii_sel register defines */ -- cgit From b4c927b33d520102deb19c318986695a8b19b467 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Wed, 11 Sep 2013 15:30:14 +0200 Subject: ARM: arch-mx6: fix PLL2_PFD2_FREQ according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000 Signed-off-by: Markus Niebel Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe60f4..2813593e25 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg { #define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000 -- cgit From 31f07964c896e19b501e9a4a59a8df85515cd0b9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 13 Sep 2013 00:36:28 -0300 Subject: mx6slevk: Add Ethernet support mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam --- arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/include/asm/arch-mx6/iomux.h | 5 +++++ arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 12 ++++++++++++ 3 files changed, 18 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index c49368765b..93f29a780f 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -50,4 +50,5 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); +int enable_fec_anatop_clock(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index f4cfd4f921..ff13a1ea9f 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -27,6 +27,11 @@ #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) +#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) +#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) +#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) + #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index b39a354f39..5f9c90ad87 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -18,5 +18,17 @@ enum { MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), + + MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), + MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), + MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), + MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), + MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), + MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ -- cgit From e654ddf7b354163d9efcfd14c6b08f9e46c0108b Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 13 Sep 2013 09:19:21 -0700 Subject: i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10 This patch fixes a regression introduced by commit 87d720e0. Signed-off-by: Eric Nelson Acked-by: Otavio Salvador --- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index c3d0b70877..ad537b4b9e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -235,7 +235,7 @@ enum { MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), @@ -309,7 +309,7 @@ enum { MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), -- cgit From 9721027aae63aab072de6ee8eae68d8e684b3af3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:46 -0400 Subject: am335x_evm: am33xx_spl_board_init function and scale core frequency Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 10 +++++++++- arch/arm/include/asm/arch-am33xx/sys_proto.h | 3 +++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 140379fb38..aad698ddfe 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -11,9 +11,17 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_550 550 +#define MPUPLL_M_300 300 + /* MAIN PLL Fdll = 550 MHz, by default */ #ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK 550 +#define CONFIG_SYS_MPUCLK MPUPLL_M_550 #endif #define UART_RESET (0x1 << 1) diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 55f57ac9be..87b7d367b9 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,6 +10,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include #define BOARD_REV_ID 0x0 @@ -43,4 +44,6 @@ u32 wait_on_value(u32, u32, void *, u32); void enable_norboot_pin_mux(void); #endif void am33xx_spl_board_init(void); +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); #endif -- cgit From 52f7d8442e0837ef00f848865286e301a5f0f78f Mon Sep 17 00:00:00 2001 From: Steve Kipisz Date: Wed, 14 Aug 2013 10:51:31 -0400 Subject: am335x:Handle worst case scenario for Errata 1.0.24 In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra Cc: Lars Poeschel Signed-off-by: Steve Kipisz [trini: Adapt to current framework] Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index aad698ddfe..02ed5957e9 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -29,5 +29,7 @@ #define UART_SMART_IDLE_EN (0x1 << 0x3) extern void enable_dmm_clocks(void); +extern const struct dpll_params dpll_core_opp100; +extern struct dpll_params dpll_mpu_opp100; #endif /* endif _CLOCKS_AM33XX_H_ */ -- cgit From e22cc0cf137149bea3a06bb29ffe06e82d8edb84 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 23 Aug 2013 17:34:17 +0530 Subject: ARM: OMAP5: Avoid writing into LDO SRAM bits Writing magic bits into LDO SRAM was suggested only for OMAP5432 ES1.0. Now these are no longer applicable. Moreover these bits should not be overwritten as they are loaded from EFUSE. So avoid writing into these registers. Boot tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/omap_common.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 5e2f027ba4..61fee9f06d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -310,12 +310,6 @@ struct prcm_regs { u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; - u32 prm_sldo_core_setup; - u32 prm_sldo_core_ctrl; - u32 prm_sldo_mpu_setup; - u32 prm_sldo_mpu_ctrl; - u32 prm_sldo_mm_setup; - u32 prm_sldo_mm_ctrl; u32 prm_abbldo_mpu_setup; u32 prm_abbldo_mpu_ctrl; -- cgit From fe1378a961e508b31b1f29a2bb08ba1dac063155 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sat, 21 Sep 2013 14:04:41 +0200 Subject: ARM: use r9 for gd To be more EABI compliant and as a preparation for building with clang, use the platform-specific r9 register for gd instead of r8. note: The FIQ is not updated since it is not used in u-boot, and under discussion for the time being. The following checkpatch warning is ignored: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt Signed-off-by: Jeroen Hofstee cc: Albert ARIBAUD --- arch/arm/include/asm/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 79a9597419..e126436093 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -47,6 +47,6 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") #endif /* __ASM_GBL_DATA_H */ -- cgit From ce7a7f5e6bda35d7d0972be07b6983552d1a2cb2 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 25 Sep 2013 08:37:44 -0700 Subject: i.MX6DQ/DLS: Add pad MX6_PAD_GPIO_1__USB_OTG_ID This patch adds the pad to i.MX6DQ and changes the i.MX6DLS declaration to match the Linux kernel declaration. Signed-off-by: Eric Nelson Acked-by: Marek Vasut --- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2 +- arch/arm/include/asm/arch-mx6/mx6q_pins.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index ad537b4b9e..b5df68afc6 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -1043,7 +1043,7 @@ enum { MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), - MX6_PAD_GPIO_1__USBOTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index 94df0075b0..fe9a8c343d 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -984,6 +984,7 @@ enum { MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), -- cgit