From 6d1970fa8a8d315af2b5c2c6f0ad5e5c24a382b5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 16:11:05 +0800 Subject: rockchip: add sdram_common for common functions There are some functions like sdram_size_mb can be re-used for different rockchip SoCs, just put them into common file. Add board_get_usable_ram_top() for ram_top init base on SDRAM_MAX_SIZE. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Added SDRAM_MAX_SIZE definition for RK3036: Signed-off-by: Philipp Tomsich fixup: 3036 fix for sdram_common --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_common.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h new file mode 100644 index 0000000000..fec85865ff --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SDRAM_COMMON_H +#define _ASM_ARCH_SDRAM_COMMON_H +/* + * sys_reg bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] cs0_row_ch1 + * [21:20] cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0 + * [8] bk_ch0 + * [7:6] cs0_row_ch0 + * [5:4] cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 +*/ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 + +/* Get sdram size decode from reg */ +size_t rockchip_sdram_size(phys_addr_t reg); + +/* Called by U-Boot board_init_r for Rockchip SoCs */ +int dram_init(void); +#endif -- cgit From 7805cdf494beb0014590b8bc79338c02c3791f15 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 16:11:06 +0800 Subject: rockchip: use common sdram function Replace the sdram_init() in board init and rockchip_sdram_size() in sdram driver for all the Rockchip SoCs which enable CONFIG_RAM. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Make dram_init() in rk3036-board.c conditional on CONFIG_RAM: Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 48 ------------------------- 1 file changed, 48 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index 9a59075afc..35696c741f 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -441,52 +441,4 @@ enum { /* mr1 for ddr3 */ #define DDR3_DLL_DISABLE 1 -/* - *TODO(sjg@chromium.org): We use a PMU register to store SDRAM information for - * passing from SPL to U-Boot. It would probably be better to use a normal C - * structure in SRAM. - * - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 - #endif -- cgit From cc89369fb0055ec34a56becd8ecc8d0b9d77c801 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 16:11:08 +0800 Subject: rockchip: rk3368: add sdram driver for U-Boot Add sdram driver in U-Boot for get the correct sdram size from sys_reg, so that U-Boot can co-work with Rockchip loader or SPL to get different dram capability and then tell the kernel. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 3233dc306e..93c4e7d4e1 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -92,8 +92,10 @@ struct rk3368_pmu_grf { u32 gpio0d_drv; u32 gpio0l_sr; u32 gpio0h_sr; + u32 reserved[(0x200 - 0x34) / 4 - 1]; + u32 os_reg[4]; }; -check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[3], 0x20c); /*GRF_GPIO0C_IOMUX*/ enum { -- cgit From 045029cbd16782031fceede2808b4905214f0921 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:49 +0800 Subject: rockchip: rk322x: add clock driver Add clock driver init support for: - cpu, bus clock init; - emmc, sdmmc clock; - ddr clock; Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Fixed format specified (%x -> %p) in clk_rk322x.c: Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h new file mode 100644 index 0000000000..2a2f804f67 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK322X_H +#define _ASM_ARCH_CRU_RK322X_H + +#include + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk322x_clk_priv { + struct rk322x_cru *cru; + ulong rate; +}; + +struct rk322x_cru { + struct rk322x_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + } pll[4]; + unsigned int reserved0[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[16]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved1[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved2[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved4[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved5[4]; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int cru_pll_mask_con; +}; +check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 13, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_HDMIPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 6, + CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_CLK_PLL_SEL_DPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLKSEL5_CON */ + GMAC_OUT_PLL_SHIFT = 15, + GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, + GMAC_OUT_DIV_SHIFT = 8, + GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, + MAC_PLL_SEL_SHIFT = 7, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + RMII_EXTCLK_SLE_SHIFT = 5, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, + RMII_EXTCLK_SEL_INT = 0, + RMII_EXTCLK_SEL_EXT, + CLK_MAC_DIV_SHIFT = 0, + CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, + PERI_PLL_SEL_SHIFT = 10, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_CPLL = 0, + PERI_PLL_GPLL, + PERI_PLL_HDMIPLL, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, + + /* CRU_CLKSEL26_CON */ + DDR_CLK_PLL_SEL_SHIFT = 8, + DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, + DDR_CLK_SEL_DPLL = 0, + DDR_CLK_SEL_GPLL, + DDR_CLK_SEL_APLL, + DDR_DIV_SEL_SHIFT = 0, + DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, + + /* CRU_CLKSEL27_CON */ + VOP_DCLK_DIV_SHIFT = 8, + VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, + VOP_PLL_SEL_SHIFT = 1, + VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, + + /* CRU_CLKSEL29_CON */ + GMAC_CLK_SRC_SHIFT = 12, + GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif -- cgit From 5cc9d31a79fecfaacfdbc9c566b6df35765100f8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:50 +0800 Subject: rockchip: rk322x: add pinctrl driver Add init pinctrl driver support for: - i2c; - spi; - uart; - pwm; - emmc/sdmmc; Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 519 ++++++++++++++++++++++++ 1 file changed, 519 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk322x.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h new file mode 100644 index 0000000000..26071c8ec8 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h @@ -0,0 +1,519 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK322X_H +#define _ASM_ARCH_GRF_RK322X_H + +#include + +struct rk322x_grf { + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + + unsigned int reserved1[4]; + unsigned int con_iomux; + unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; + unsigned int gpio0_p[4]; + unsigned int gpio1_p[4]; + unsigned int gpio2_p[4]; + unsigned int gpio3_p[4]; + unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; + unsigned int gpio0_e[4]; + unsigned int gpio1_e[4]; + unsigned int gpio2_e[4]; + unsigned int gpio3_e[4]; + unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; + unsigned int soc_con[7]; + unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; + unsigned int soc_status[3]; + unsigned int chip_id; + unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; + unsigned int cpu_con[4]; + unsigned int reserved7[4]; + unsigned int cpu_status[2]; + unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; + unsigned int os_reg[8]; + unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; + unsigned int ddrc_stat; +}; +check_member(rk322x_grf, ddrc_stat, 0x604); + +struct rk322x_sgrf { + unsigned int soc_con[11]; + unsigned int busdmac_con[4]; +}; + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + GPIO0A7_HDMI_DDCSDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + GPIO0A6_HDMI_DDCSCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + GPIO0A3_SDIO_CMD, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B7_SHIFT = 14, + GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, + GPIO0B7_GPIO = 0, + GPIO0B7_HDMI_HDP, + + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S1_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S_MCLK, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_HDMI_CECSDA, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_RSTN, + GPIO0C1_CLK_OUT1, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDIO_PWREN, + GPIO0D6_PWM11, + + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 1, + GPIO1A7_GPIO = 0, + GPIO1A7_SDMMC_WRPRT, +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_SDMMC_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_SDMMC_PWREN, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_SPI_CSN1, + GPIO1B4_PWM12, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_UART1_RSTN, + GPIO1B3_PWM13, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_NAND_CS3, + GPIO1C7_EMMC_RSTNOUT, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_SDMMC_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_SDMMC_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_SDMMC_D1, + GPIO1C3_UART2_SIN, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , + GPIO1C2_GPIO = 0, + GPIO1C2_SDMMC_D0, + GPIO1C2_UART2_SOUT, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_SDMMC_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_SDMMC_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SPI1_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SPI1_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_SPI1_TXD, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI1_RXD, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_GMAC_CLK, + GPIO2B6_MAC_LINK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_GMAC_TXCLK, + + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_GMAC_RXDV, + GPIO2B0_MAC_SPEED_IOUT, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + GPIO2C4_GMAC_RXD3, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_GMAC_COL, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_DRV_VBUS1, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_PWM10, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_DRV_VBUS, +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_PWM3, +}; + +/* GRF_CON_IOMUX */ +enum { + CON_IOMUX_GMAC_SHIFT = 15, + CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT, + CON_IOMUX_UART1SEL_SHIFT = 11, + CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, + CON_IOMUX_UART2SEL_SHIFT = 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + CON_IOMUX_EMMCSEL_SHIFT = 7, + CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, + CON_IOMUX_PWM3SEL_SHIFT = 3, + CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, + CON_IOMUX_PWM2SEL_SHIFT = 2, + CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, + CON_IOMUX_PWM1SEL_SHIFT = 1, + CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, + CON_IOMUX_PWM0SEL_SHIFT = 0, + CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, +}; +#endif -- cgit From 168eef7ada98c6bff53458013e42cdbc5adb3cd4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:52 +0800 Subject: rockchip: rk322x: add basic soc support Enable soc support for SPL and U-boot skeleton. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index b06bb6c9ec..641df58ac2 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -19,6 +19,7 @@ enum { ROCKCHIP_SYSCON_PMUGRF, ROCKCHIP_SYSCON_PMUSGRF, ROCKCHIP_SYSCON_CIC, + ROCKCHIP_SYSCON_MSCH, }; /* Standard Rockchip clock numbers */ -- cgit From e3ef41df480f5c0da2d3d40ec2207e210bd34419 Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Mon, 19 Jun 2017 14:45:36 +0800 Subject: rockchip: pwm: fix the register layout for the PWM controller According to rk3288 spec, the pwm register order is: PWM_PWM0_CNT, PWM_PWM0_PERIOD_HPR, PWM_PWM0_DUTY_LPR, PWM_PWM0_CTRL but the source code's order is: struct rk3288_pwm { u32 cnt; u32 duty_lpr; u32 period_hpr; u32 ctrl; }; So, correct it here. It is the same as RK3399. Signed-off-by: Eric Gao Edited the commit message: Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/pwm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h index 5d9a178a70..08ff94591c 100644 --- a/arch/arm/include/asm/arch-rockchip/pwm.h +++ b/arch/arm/include/asm/arch-rockchip/pwm.h @@ -10,8 +10,8 @@ struct rk3288_pwm { u32 cnt; - u32 duty_lpr; u32 period_hpr; + u32 duty_lpr; u32 ctrl; }; check_member(rk3288_pwm, ctrl, 0xc); -- cgit From 2454b719fb874120e06e4aa64bfb9450d091e56c Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 26 Jun 2017 10:01:46 +0200 Subject: rockchip: rk3288: Add pinctrl support for the gmac ethernet interface Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 boards, using the RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO. Signed-off-by: Sjoerd Simons Signed-off-by: Romain Perier Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 178 ++++++++++++++++++++++++ 1 file changed, 178 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index fbc4a0d80f..818e4c5666 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -283,6 +283,163 @@ enum { GPIO3C0_EMMC_CMD, }; +/* GRF_GPIO3DL_IOMUX */ +enum { + GPIO3D3_SHIFT = 12, + GPIO3D3_MASK = 7, + GPIO3D3_GPIO = 0, + GPIO3D3_FLASH1_DATA3, + GPIO3D3_HOST_DOUT3, + GPIO3D3_MAC_RXD3, + GPIO3D3_SDIO1_DATA3, + + GPIO3D2_SHIFT = 8, + GPIO3D2_MASK = 7, + GPIO3D2_GPIO = 0, + GPIO3D2_FLASH1_DATA2, + GPIO3D2_HOST_DOUT2, + GPIO3D2_MAC_RXD2, + GPIO3D2_SDIO1_DATA2, + + GPIO3D1_SHIFT = 4, + GPIO3D1_MASK = 7, + GPIO3D1_GPIO = 0, + GPIO3DL1_FLASH1_DATA1, + GPIO3D1_HOST_DOUT1, + GPIO3D1_MAC_TXD3, + GPIO3D1_SDIO1_DATA1, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 7, + GPIO3D0_GPIO = 0, + GPIO3D0_FLASH1_DATA0, + GPIO3D0_HOST_DOUT0, + GPIO3D0_MAC_TXD2, + GPIO3D0_SDIO1_DATA0, +}; + +/* GRF_GPIO3HL_IOMUX */ +enum { + GPIO3D7_SHIFT = 12, + GPIO3D7_MASK = 7, + GPIO3D7_GPIO = 0, + GPIO3D7_FLASH1_DATA7, + GPIO3D7_HOST_DOUT7, + GPIO3D7_MAC_RXD1, + GPIO3D7_SDIO1_INTN, + + GPIO3D6_SHIFT = 8, + GPIO3D6_MASK = 7, + GPIO3D6_GPIO = 0, + GPIO3D6_FLASH1_DATA6, + GPIO3D6_HOST_DOUT6, + GPIO3D6_MAC_RXD0, + GPIO3D6_SDIO1_BKPWR, + + GPIO3D5_SHIFT = 4, + GPIO3D5_MASK = 7, + GPIO3D5_GPIO = 0, + GPIO3D5_FLASH1_DATA5, + GPIO3D5_HOST_DOUT5, + GPIO3D5_MAC_TXD1, + GPIO3D5_SDIO1_WRPRT, + + GPIO3D4_SHIFT = 0, + GPIO3D4_MASK = 7, + GPIO3D4_GPIO = 0, + GPIO3D4_FLASH1_DATA4, + GPIO3D4_HOST_DOUT4, + GPIO3D4_MAC_TXD0, + GPIO3D4_SDIO1_DETECTN, +}; + +/* GRF_GPIO4AL_IOMUX */ +enum { + GPIO4A3_SHIFT = 12, + GPIO4A3_MASK = 7, + GPIO4A3_GPIO = 0, + GPIO4A3_FLASH1_ALE, + GPIO4A3_HOST_DOUT9, + GPIO4A3_MAC_CLK, + GPIO4A3_FLASH0_CSN6, + + GPIO4A2_SHIFT = 8, + GPIO4A2_MASK = 7, + GPIO4A2_GPIO = 0, + GPIO4A2_FLASH1_RDN, + GPIO4A2_HOST_DOUT8, + GPIO4A2_MAC_RXER, + GPIO4A2_FLASH0_CSN5, + + GPIO4A1_SHIFT = 4, + GPIO4A1_MASK = 7, + GPIO4A1_GPIO = 0, + GPIO4A1_FLASH1_WP, + GPIO4A1_HOST_CKOUTN, + GPIO4A1_MAC_TXDV, + GPIO4A1_FLASH0_CSN4, + + GPIO4A0_SHIFT = 0, + GPIO4A0_MASK = 3, + GPIO4A0_GPIO = 0, + GPIO4A0_FLASH1_RDY, + GPIO4A0_HOST_CKOUTP, + GPIO4A0_MAC_MDC, +}; + +/* GRF_GPIO4AH_IOMUX */ +enum { + GPIO4A7_SHIFT = 12, + GPIO4A7_MASK = 7, + GPIO4A7_GPIO = 0, + GPIO4A7_FLASH1_CSN1, + GPIO4A7_HOST_DOUT13, + GPIO4A7_MAC_CSR, + GPIO4A7_SDIO1_CLKOUT, + + GPIO4A6_SHIFT = 8, + GPIO4A6_MASK = 7, + GPIO4A6_GPIO = 0, + GPIO4A6_FLASH1_CSN0, + GPIO4A6_HOST_DOUT12, + GPIO4A6_MAC_RXCLK, + GPIO4A6_SDIO1_CMD, + + GPIO4A5_SHIFT = 4, + GPIO4A5_MASK = 3, + GPIO4A5_GPIO = 0, + GPIO4A5_FLASH1_WRN, + GPIO4A5_HOST_DOUT11, + GPIO4A5_MAC_MDIO, + + GPIO4A4_SHIFT = 0, + GPIO4A4_MASK = 7, + GPIO4A4_GPIO = 0, + GPIO4A4_FLASH1_CLE, + GPIO4A4_HOST_DOUT10, + GPIO4A4_MAC_TXEN, + GPIO4A4_FLASH0_CSN7, +}; + +/* GRF_GPIO4BL_IOMUX */ +enum { + GPIO4B1_SHIFT = 4, + GPIO4B1_MASK = 7, + GPIO4B1_GPIO = 0, + GPIO4B1_FLASH1_CSN2, + GPIO4B1_HOST_DOUT15, + GPIO4B1_MAC_TXCLK, + GPIO4B1_SDIO1_PWREN, + + GPIO4B0_SHIFT = 0, + GPIO4B0_MASK = 7, + GPIO4B0_GPIO = 0, + GPIO4B0_FLASH1_DQS, + GPIO4B0_HOST_DOUT14, + GPIO4B0_MAC_COL, + GPIO4B0_FLASH1_CSN3, +}; + /* GRF_GPIO4C_IOMUX */ enum { GPIO4C7_SHIFT = 14, @@ -886,4 +1043,25 @@ enum GRF_SOC_CON8 { RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, }; +/* GPIO Bias settings */ +enum GPIO_BIAS { + GPIO_BIAS_2MA = 0, + GPIO_BIAS_4MA, + GPIO_BIAS_8MA, + GPIO_BIAS_12MA, +}; + +#define GPIO_BIAS_MASK 0x3 +#define GPIO_BIAS_SHIFT(x) ((x) * 2) + +enum GPIO_PU_PD { + GPIO_PULL_NORMAL = 0, + GPIO_PULL_UP, + GPIO_PULL_DOWN, + GPIO_PULL_REPEAT, +}; + +#define GPIO_PULL_MASK 0x3 +#define GPIO_PULL_SHIFT(x) ((x) * 2) + #endif -- cgit