From e332623b0328f91c76d99c356c350fc04b1fc8dc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:27 +0800 Subject: imx: mx6sl: add lcdif clock support Add lcdif clock support for i.MX6SL. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx6/crm_regs.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 29674ce54d..74ed91230f 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -307,6 +307,9 @@ struct mxc_ccm_reg { /* LCFIF2_PODF on i.MX6SX */ #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 +/* LCDIF_PIX_PODF on i.MX6SL */ +#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20 /* ACLK_EMI on i.MX6DQ/SDL/DQP */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 @@ -529,6 +532,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 +/*LCD on i.MX6SL */ +#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3 + /* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 @@ -554,6 +563,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 +/* For i.MX6SL */ +#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 +#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 + /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) @@ -783,6 +798,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_QSPI_OFFSET 14 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) +/* i.MX6SL */ +#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) + #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 -- cgit