From e7ab6dfc65f3656bf0df9e818dc12ad33be26d44 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 18 Dec 2018 17:52:06 +0800 Subject: poplar: add DWC2 OTG gadget support It enables DWC2 OTG gadget driver support for Poplar board. As usb2_phy_init() is being always called from board_init(), we can save the call from board_usb_init(). Signed-off-by: Shawn Guo --- arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h index f97b1eb29f..bb221e17e0 100644 --- a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -13,11 +13,16 @@ /* DEVICES */ #define REG_BASE_MCI 0xF9830000 #define REG_BASE_UART0 0xF8B00000 +#define HIOTG_BASE_ADDR 0xF98C0000 /* PERI control registers (4KB) */ /* USB2 PHY01 configuration register */ #define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) + /* USB2 controller configuration register */ +#define PERI_CTRL_USB3 (REG_BASE_PERI_CTRL + 0x12c) +#define USB2_2P_CHIPID (1 << 28) + /* PERI CRG registers (4KB) */ /* USB2 CTRL0 clock and soft reset */ #define PERI_CRG46 (REG_BASE_CRG + 0xb8) -- cgit From 3e066bcaefb51adcf5c0594d42abe145f701dbeb Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Thu, 20 Dec 2018 16:12:51 +0800 Subject: reset: MedaiTek: add reset controller driver for MediaTek SoCs This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee Signed-off-by: Weijie Gao --- arch/arm/include/asm/arch-mediatek/reset.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm/include/asm/arch-mediatek/reset.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-mediatek/reset.h b/arch/arm/include/asm/arch-mediatek/reset.h new file mode 100644 index 0000000000..9704666d24 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_RESET_H +#define __MEDIATEK_RESET_H + +#include + +int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs); + +#endif /* __MEDIATEK_RESET_H */ -- cgit