From af104ae5b87c8efb107ac282d09927d8346dc94f Mon Sep 17 00:00:00 2001 From: Eran Matityahu Date: Thu, 14 Dec 2017 20:20:02 +0200 Subject: imx: spl: Fix NAND bootmode detection commit 20f14714169 ("imx: spl: Update NAND bootmode detection bit") broke the NAND bootmode detection by checking if BOOT_CFG1[7:4] == 0x8 for NAND boot mode. This commit essentially reverts it, while using the IMX6_BMODE_* macros that were introduced since. Tables 8-7 & 8-10 from IMX6DQRM say the NAND boot mode selection is done when BOOT_CFG1[7] is 1, but BOOT_CFG1[6:4] is not necessarily 0x0 in this case. Actually, NAND boot mode is when 0x8 <= BOOT_CFG1[7:4] <= 0xf, like it was in the code before. Signed-off-by: Eran Matityahu Cc: Stefano Babic Cc: Jagan Teki Cc: Tim Harvey --- arch/arm/include/asm/mach-imx/sys_proto.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 5184e00972..d518e03809 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -81,7 +81,8 @@ enum imx6_bmode { IMX6_BMODE_ESD, IMX6_BMODE_MMC, IMX6_BMODE_EMMC, - IMX6_BMODE_NAND, + IMX6_BMODE_NAND_MIN, + IMX6_BMODE_NAND_MAX = 0xf, }; static inline u8 imx6_is_bmode_from_gpr9(void) -- cgit From 290e7cfdbfa288d26598c073186ab45e3fa711b3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Jan 2018 12:33:05 -0200 Subject: mx6ull: Handle the CONFIG_MX6ULL cases correctly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 051ba9e082f7 ("Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so take this into consideration in all the checks for CONFIG_MX6UL. This fixes a boot regression. Reported-by: Stefan Agner Signed-off-by: Fabio Estevam Reviewed-by: Stefan Agner Tested-by: Breno Lima Tested-by: Peng Fan Reviewed-by: Stefano Babic Tested-by: Jörg Krause --- arch/arm/include/asm/arch-mx6/imx-regs.h | 23 +++++++++++++---------- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +- arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 2 +- arch/arm/include/asm/mach-imx/iomux-v3.h | 4 ++-- arch/arm/include/asm/mach-imx/regs-lcdif.h | 19 +++++++++++++------ 5 files changed, 30 insertions(+), 20 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7736b6a8ac..4be7aab18a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -17,7 +17,7 @@ #define GPU_2D_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_END_ADDR 0x02207FFF -#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00107FFF #define GPU_ARB_BASE_ADDR 0x01800000 @@ -46,7 +46,8 @@ #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ +#if (defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) #define GPV2_BASE_ADDR 0x00D00000 #define GPV3_BASE_ADDR 0x00E00000 @@ -88,7 +89,7 @@ #define QSPI0_AMBA_END 0x6FFFFFFF #define QSPI1_AMBA_BASE 0x70000000 #define QSPI1_AMBA_END 0x7FFFFFFF -#elif defined(CONFIG_MX6UL) +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF #define QSPI0_AMBA_BASE 0x60000000 @@ -109,7 +110,8 @@ #endif #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) + defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -262,7 +264,7 @@ #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) /* i.MX6SL/SLL */ #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#ifdef CONFIG_MX6UL +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #else /* i.MX6SX */ @@ -288,7 +290,7 @@ #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#ifdef CONFIG_MX6UL +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #elif defined(CONFIG_MX6SX) @@ -337,7 +339,7 @@ #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) -#elif defined(CONFIG_MX6ULL) +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) @@ -354,7 +356,8 @@ #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ +#if !(defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) #define IRAM_SIZE 0x00040000 #else @@ -573,7 +576,7 @@ struct src { #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) struct iomuxc { -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) u8 reserved[0x4000]; #endif u32 gpr[14]; @@ -700,7 +703,7 @@ struct cspi_regs { #define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) + defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 2a8d4431ea..19d2f1d9c5 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -16,7 +16,7 @@ #ifdef CONFIG_MX6SX #include "mx6sx-ddr.h" #else -#ifdef CONFIG_MX6UL +#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #include "mx6ul-ddr.h" #else #ifdef CONFIG_MX6SL diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h index ed11c4bb4d..518b81208a 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_MX6UL_DDR_H__ #define __ASM_ARCH_MX6UL_DDR_H__ -#ifndef CONFIG_MX6UL +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) #error "wrong CPU" #endif diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index ad35e0109e..ed75e9cd9a 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -127,7 +127,7 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_ODE (1 << 11) -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define PAD_CTL_SPEED_LOW (0 << 6) #else #define PAD_CTL_SPEED_LOW (1 << 6) @@ -253,7 +253,7 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \ imx_iomux_v3_setup_pad(MX6Q_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) -#elif defined(CONFIG_MX6UL) +#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) #define IOMUX_PADS(x) MX6_##x #define SETUP_IOMUX_PAD(def) \ imx_iomux_v3_setup_pad(MX6_##def); diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index 4de401bd22..c6cf03bf5a 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -19,8 +19,11 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ -#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) + +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -55,8 +58,10 @@ struct mxs_lcdif_regs { #endif mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ -#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -64,8 +69,10 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) +#if defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) -- cgit From 46718353b2fc784fa8f658fd5112272ed921ce9a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 5 Jan 2018 15:08:19 +0100 Subject: imx: initialize and use generic timer on i.MX 6UL/ULL The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM generic timer. This change makes use of the ARM generic timer in U-Boot. This is crucial to make the ARM generic timers usable in Linux since timer_init() initalizes the system counter module, which is necessary to use the generic timers CP15 registers. Signed-off-by: Stefan Agner Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4be7aab18a..48ce0edd06 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -291,6 +291,7 @@ #endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #elif defined(CONFIG_MX6SX) -- cgit